Search Results - Processors—compilers Algorithms

shade.js: Adaptive Material Descriptions by Sons, Kristian, Klein, Felix, Sutter, Jan, Slusallek, Philipp

“…In computer graphics a material is a visual concept that is parameterizable and should work for arbitrary 3D assets and rendering systems. Since provided…”
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Optimizing shared cache behavior of chip multiprocessors by Kandemir, Mahmut, Muralidhara, Sai Prashanth, Narayanan, Sri Hari Krishna, Zhang, Yuanrui, Ozturk, Ozcan

“…One of the critical problems associated with emerging chip multiprocessors (CMPs) is the management of on-chip shared cache space. Unfortunately, single…”
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ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design by Zheng, Jianwei, Liu, Yu, Liu, Xuejiao, Liang, Luhong, Chen, Deming, Cheng, Kwang-Ting

“… In this paper, we propose a compiler-architecture co-design scheme targeting a reconfigurable and algorithm-oriented array processor, named ReAAP…”
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Software based techniques for robust computing on Chip Multiprocessors by Narayanan, Sri Hari Krishna

“…Robustness and performance are two requirements of any computing system. They may be quantified by different metrics depending on the domain of Computer…”
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Data flow anomaly detection of recursive procedures by Livadas, Panos E., Qi Tsao, Qing

“…Let P be a program and v be a variable of P; let G p be the flowgraph of P; and, let p 1 , be a node in G P that corresponds to a point in P where a variable v…”
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SoftExplorer: Estimating and Optimizing the Power and Energy Consumption of a C Program for DSP Applications by Senn, Eric, Laurent, Johann, Julien, Nathalie, Martin, Eric

“… Three models are involved: a model for the targeted processor the power model), a model for the algorithm, and a model for the compiler…”
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Embedded Processor Oriented Compiler Infrastructure by DJUKIC, M., POPOVIC, M., CETIC, N., POVAZAN, I.

“…In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures…”
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A methodology for speeding up loop kernels by exploiting the software information and the memory architecture by Kelefouras, Vasilios, Kritikakou, Angeliki, Goutis, Costas

“… Second, they take into account only part of the specific algorithm׳s information. Third, they take into account only a few hardware architecture parameters…”
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System dynamics monitoring using PIC micro-controller-based PLSE by Djeufa Dagoumguei, Guy Morgand, Tagne, Samuel, Eyebe Fouda, J S Armand, Koepf, Wolfram

“… The PLSE algorithm is optimized to fit the program and data memory of low-end processors using the XC8 compiler and the MPLAB X IDE…”
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Tensor Instruction Generation Optimization Fusing with Loop Partitioning by Liang, Jiali, Hua, Baojian, Su, Shaobo

“…The tensor compiler compiles the tensor algorithm and schedule of the operator into the code of the target…”
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Soft Error Reliability Assessment of Lightweight Cryptographic Algorithms for IoT Edge Devices by Rocha, Vinicius Da, Moura, Nicolas, Gava, Jonas, Bandeira, Vitor, Ost, Luciano, Reis, Ricardo, Garibotti, Rafael

“… This paper performs soft error analysis for ten lightweight cryptographic algorithms considering two compilers and running on top of an IoT-ready commercial processor model (i.e. Arm Cortex-M7…”
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Understand Code Style: Efficient CNN-Based Compiler Optimization Recognition System by Yang, Shouguo, Shi, Zhiqiang, Zhang, Guodong, Li, Mingxuan, Ma, Yuan, Sun, Limin

“… There are thousands of compiler optimization algorithms and multiple different processor architectures, so it is very difficult to manually analyze binary files and recognize its compiler optimization level with rules…”
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Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors by Danbee Park, Jungseob Lee, Nam Sung Kim, Taewhan Kim

“… Precisely, based on an execution profile of code containing conditional branches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions…”
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Efficient methodology for hand-coding video algorithms for VLIW-type processors by Sohm, Oliver P., Bull, David R., Canagarajah, C.Nishan

“… Although sophisticated compilers are available for VLIW-type processors, time-critical video coding algorithms can often be more efficiently coded by hand…”
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Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors by Kim, Hyesoon, Joao, José A., Mutlu, Onur, Patt, Yale N.

“… This paper describes compiler support for obtaining high performance in the diverge-merge processor…”
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RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors by Akturan, Cagdas, Jacome, Margarida F.

“…), suitable for optimizing compilers targeting embedded VLIW processors. The key difference between RS-FDRA and previous approaches is that our algorithm can handle code size constraints along with latency and resource constraints…”
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Loop scheduling for heterogeneity by Cierniak, M., Wei Li, Zaki, M.J.

“…, and develop compiler algorithms for generating optimal and sub-optimal schedules of loops for load…”
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Exploiting Computation Reuse for Stencil Accelerators by Chi, Yuze, Cong, Jason

“…Stencil kernel is an important type of kernel used extensively in many application domains. Over the years, researchers have been studying the optimizations on…”
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A methodology correlating code optimizations with data memory accesses, execution time and energy consumption by Kelefouras, Vasilios, Djemame, Karim

“…) and algorithm characteristics (e.g., data reuse); therefore, compiler designers and researchers either do not take them into account at all or…”
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Improving cache locality by a combination of loop and data transformations by Kandemir, M., Ramanujam, J., Choudhary, A.

“… This paper describes a compiler algorithm for optimizing cache locality in scientific codes on uniprocessor and multiprocessor machines…”
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