Search Results - Engineering::Computer science and engineering::Hardware::Integrated circuits

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration by Genc, Hasan, Kim, Seah, Amid, Alon, Haj-Ali, Ameer, Iyer, Vighnesh, Prakash, Pranav, Zhao, Jerry, Grubb, Daniel, Liew, Harrison, Mao, Howard, Ou, Albert, Schmidt, Colin, Steffl, Samuel, Wright, John, Stoica, Ion, Ragan-Kelley, Jonathan, Asanovic, Krste, Nikolic, Borivoje, Shao, Yakun Sophia

“…DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This…”
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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits by Wu, Tony F., Ganesan, Karthik, Hu, Yunqing Alexander, Wong, H.-S. Philip, Wong, Simon, Mitra, Subhasish

“…There are increasing concerns about possible malicious modifications of integrated circuits (ICs…”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks by Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“… In this paper we design and implement Caffeine, a hardware/software co-designed library to efficiently accelerate the entire CNN on FPGAs…”
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Hardware Private Circuits: From Trivial Composition to Full Verification by Cassiers, Gaetan, Gregoire, Benjamin, Levi, Itamar, Standaert, Francois-Xavier

“… We show that the resulting "Hardware Private Circuits" approach the implementation…”
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Custom Hardware Architectures for Deep Learning on Portable Devices: A Review by Zaman, Kh Shahriya, Reaz, Mamun Bin Ibne, Md Ali, Sawal Hamid, Bakar, Ahmad Ashrif A, Chowdhury, Muhammad Enamul Hoque

“…The staggering innovations and emergence of numerous deep learning (DL) applications have forced researchers to reconsider hardware architecture to accommodate fast and efficient application-specific computations…”
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Hardware Trojan Attacks: Threat Analysis and Countermeasures by Bhunia, Swarup, Hsiao, Michael S., Banga, Mainak, Narasimhan, Seetharam

“…Security of a computer system has been traditionally related to the security of the software or the information being processed…”
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HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network by Xiao, Jie, Chai, Shuiliang, Gao, Yanjiao, Huang, Yuhao, Zhang, Fan, Chen, Tieming

“…Hardware Trojans (HTs) present significant security threats to integrated circuits…”
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CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator by Sunny, Febin, Mirza, Asif, Nikdast, Mahdi, Pasricha, Sudeep

“… CrossLight includes device-level engineering for resilience to process variations and thermal crosstalk, circuit-level tuning enhancements for inference latency reduction, and architecture-level…”
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QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code by Ueno, Yosuke, Kondo, Masaaki, Tanaka, Masamitsu, Suzuki, Yasunari, Tabuchi, Yutaka

“… In this paper, we propose an online-QEC algorithm and its hardware implementation with SFQ based superconducting digital circuits…”
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An Efficient Algorithm for Sparse Quantum State Preparation by Gleinig, Niels, Hoefler, Torsten

“…Generating quantum circuits that prepare specific states is an essential part of quantum compilation…”
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A Primer on Hardware Security: Models, Methods, and Metrics by Rostami, Masoud, Koushanfar, Farinaz, Karri, Ramesh

“…The multinational, distributed, and multistep nature of integrated circuit (IC) production supply chain has introduced hardware-based vulnerabilities…”
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Ending Piracy of Integrated Circuits by Roy, J A, Koushanfar, F, Markov, I L

“…An effective technique to combat IC piracy is to render infringement impractical by making physical tampering unprofitable and attacks computationally…”
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Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test by Afacan, Engin, Lourenço, Nuno, Martins, Ricardo, Dündar, Günhan

“… This trend has also inspired researchers working on integrated circuit (IC) design and optimization…”
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Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits by Cunxi Yu, Xiangyu Zhang, Duo Liu, Ciesielski, Maciej, Holcomb, Daniel

“…Layout-level gate or routing camouflaging techniques have attracted interest as countermeasures against reverse engineering of combinational logic…”
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Fault Analysis-Based Logic Encryption by Rajendran, Jeyavijayan, Zhang, Huan, Zhang, Chi, Rose, Garrett S., Pino, Youngok, Sinanoglu, Ozgur, Karri, Ramesh

“…Globalization of the integrated circuit (IC) design industry is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware Trojans…”
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Advanced Equivalence Checking for Quantum Circuits by Burgholzer, Lukas, Wille, Robert

“…In the not-so-distant future, quantum computing will change the way we tackle certain problems. It promises to dramatically speed-up many chemical, financial,…”
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DEFending Integrated Circuit Layouts by Bhandari, Jitendra, Gopinath, Jayanth, Ashraf, Mohammed, Knechtel, Johann, Sinanoglu, Ozgur, Karri, Ramesh

“…Modern integrated circuits (ICs) require a complex, outsourced supply-chain, involving computer-aided design (CAD…”
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LLMCompass: Enabling Efficient Hardware Design for Large Language Model Inference by Zhang, Hengrui, Ning, August, Prabhakar, Rohan Baskar, Wentzlaff, David

“…The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded their broader adoption, calling for efficient hardware designs…”
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Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications by Ferrandi, Fabrizio, Castellana, Vito Giovanni, Curzel, Serena, Fezzardi, Pietro, Fiorito, Michele, Lattuada, Marco, Minutoli, Marco, Pilato, Christian, Tumeo, Antonino

“… Bambu provides a research environment to experiment with new ideas across HLS, high-level verification and debugging, FPGA/ASIC design, design flow space exploration, and parallel hardware accelerator design…”
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Three-dimensional integrated circuits by Topol, A. W., Tulipe, D. C. La, Shi, L., Frank, D. J., Bernstein, K., Steen, S. E., Kumar, A., Singco, G. U., Young, A. M., Guarini, K. W., Ieong, M.

“…Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density…”
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