Search Results - Engineering::Computer science and engineering::Hardware::Arithmetic and logic structures

Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization by Coward, Samuel, Drane, Theo, Constantinides, George A.

“…Data-dependent constraints commonly occur across hardware and software, often in the form of code branches or input constraints…”
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Evaluation of Binary Decision Diagrams Complexity using Relative Arithmetic Width by Radmanovic, Milos

“…Many logic synthesis methods are based on the optimization of reduced order Binary Decision Diagrams (BDDs…”
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Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method by Xie, Jiafeng, He, Pengzhou, Wen, Wujie

“…: (i) an algorithm-hardware co-design driven derivation of the proposed LUT-like method is provided detailedly for the key arithmetic of the BRLWE scheme; (ii…”
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A Survey of Approximate Computing: From Arithmetic Units Design to High-Level Applications by Que, Hao-Hua, Jin, Yu, Wang, Tong, Liu, Ming-Kai, Yang, Xing-Hua, Qiao, Fei

“…Realizing a high-performance and energy-efficient circuit system is one of the critical tasks for circuit designers. Conventional researchers always…”
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An efficient fault-tolerant arithmetic logic unit using a novel fault-tolerant 5-input majority gate in quantum-dot cellular automata by Ahmadpour, Seyed-Sajad, Mosleh, Mohammad, Heikalabad, Saeed Rasouli

“… It also shows good tolerance against cell displacement defects. Moreover, the functionality of the proposed structure is confirmed by physical proofs…”
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Modeling and simulation of FIR filter using distributed arithmetic algorithm on FPGA by Rai, Amrita, Roy, Ajay, Qamar, Shamimul, Saif, Abdulelah G. F., Hamoda, Magdi Mohammad, Azeem, Abdul, Mohammed, Salman Arafath

“…). The proposed FIR filter is implemented in high-density field programmable logic devices (FPGAs) and designed using very high-speed integrated circuit hardware description language…”
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Automatic Sparse Connectivity Learning for Neural Networks by Tang, Zhimin, Luo, Linkai, Xie, Bike, Zhu, Yiyu, Zhao, Rujie, Bi, Lvqing, Lu, Chao

“…Since sparse neural networks usually contain many zero weights, these unnecessary network connections can potentially be eliminated without degrading network…”
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CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems by Ullah, Salim, Sahoo, Siva Satyendra, Kumar, Akash

“… In recent years, Approximate Computing has emerged as a viable tool for improving the performance by utilizing reduced precision data structures and resource-optimized high-performance arithmetic operators…”
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A lightweight convolutional neural network hardware implementation for wearable heart rate anomaly detection by Gu, Minghong, Zhang, Yuejun, Wen, Yongzhong, Ai, Guangpeng, Zhang, Huihong, Wang, Pengjun, Wang, Guoqing

“…In this article, we propose a lightweight and competitively accurate heart rhythm abnormality classification model based on classical convolutional neural networks in deep neural networks and hardware…”
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Verification of gate-level arithmetic circuits by function extraction by Ciesielski, Maciej, Cunxi Yu, Brown, Walter, Duo Liu, Rossi, Andre

“…The paper presents an algebraic approach to functional verification of gate-level, integer arithmetic circuits…”
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Digit-Serial DA-Based Fixed-Point RNNs: A Unified Approach for Enhancing Architectural Efficiency by Khan, Mohd Tasleem, Alhartomi, Mohammed A.

“…) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC…”
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An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing by Liu, Yidong, Liu, Leibo, Lombardi, Fabrizio, Han, Jie

“… In this SC-RNN, a hybrid structure is developed by utilizing SC designs and binary circuits to improve the hardware efficiency without significant loss of accuracy…”
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Logic encryption: a fault analysis perspective by Rajendran, Jeyavijayan, Pino, Youngok, Sinanoglu, Ozgur, Karri, Ramesh

“…The globalization of Integrated Circuit (IC) design flow is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware trojans…”
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An Efficient Polynomial Multiplication Accelerator for Lattice-Based Cryptography With a 2-D Winograd-Based Divide-and-Conquer Method by Wang, Jianfei, Zhou, Zhen, Zhang, Fahong, Meng, Yishuo, Hou, Jia, Tang, Xin, Yang, Chen

“…Polynomial multiplication over rings constitutes one of the most computationally expensive operations in lattice-based cryptography. To accelerate it, the…”
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Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs by Pimentel, Jon J., Bohnenstiehl, Brent, Baas, Bevan M.

“…Hybrid floating-point (FP) implementations improve software FP performance without incurring the area overhead of full hardware FP units…”
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Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits by Khajehnasir-Jahromi, Hamideh, Torkzadeh, Pooya, Dousti, Massoud

“… The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder…”
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QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models by Zhang, Shen, Ning, Bin, Yan, Guangyao, Liu, Xinzhe, Jiang, Weixiong, Ha, Yajun

“… First, we reformulate the irregular model structure into a unified format, as irregular structures are inefficient for hardware implementation…”
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Uint-Packing: Multiply Your DNN Accelerator Performance via Unsigned Integer DSP Packing by Zhang, Jingwei, Zhang, Meng, Cao, Xinye, Li, Guoqing

“… Guided by this generalization model, we design the novel computational structure of the DNN accelerator…”
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ESBMC 5.0: An Industrial-Strength C Model Checker by Gadelha, Mikhail R., Monteiro, Felipe R., Morse, Jeremy, Cordeiro, Lucas C., Fischer, Bernd, Nicole, Denis A.

“…) and user-defined program assertions automatically. ESBMC provides C++ and Python APIs to access internal data structures, allowing inspection and extension at any stage of the verification process…”
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Design and Implementation of High-Speed Carry Look-Ahead Decimal Adder (CLDA) Using CMOS Technology by Al Share, Abdelsalam, Al-Khaleel, Osama, Zghoul, Fadi Nessir, Al-Khaleel, Mohammad, Papachristou, Chris

“… Hardware implementations of decimal arithmetic are preferable over their software counterparts as the former leads in performance especially when it comes to real-time applications…”
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