Search Results - Computing methodologies → Massively parallel algorithms
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Skywalker: Efficient Alias-Method-Based Graph Sampling and Random Walk on GPUs
Published: IEEE 01.09.2021Published in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…Graph sampling and random walk operations, capturing the structural properties of graphs, are playing an important role today as we cannot directly adopt computing-intensive algorithms on large-scale graphs…”
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SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs
Published: IEEE 05.12.2021Published in 2021 58th ACM/IEEE Design Automation Conference (DAC) (05.12.2021)“…Sparse LU factorization is one of the key building blocks of sparse direct solvers and often dominates the computing time of circuit simulation programs…”
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MAD-Max Beyond Single-Node: Enabling Large Machine Learning Model Acceleration on Distributed Systems
Published: IEEE 29.06.2024Published in 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Training and deploying large-scale machine learning models is time-consuming, requires significant distributed computing infrastructures, and incurs high operational costs…”
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Parallelizing Maximal Clique Enumeration on GPUs
Published: IEEE 21.10.2023Published in 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“…We present a GPU solution for exact maximal clique enumeration (MCE) that performs a search tree traversal following the Bron-Kerbosch algorithm…”
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Leveraging Difference Recurrence Relations for High-Performance GPU Genome Alignment
Published: ACM 13.10.2024Published in 2024 33rd International Conference on Parallel Architectures and Compilation Techniques (PACT) (13.10.2024)“… while decreasing the associated cost, emphasizing the need for fast and accurate software to perform sequence analysis, given the quadratic complexity of exact pairwise algorithms…”
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pSyncPIM: Partially Synchronous Execution of Sparse Matrix Operations for All-Bank PIM Architectures
Published: IEEE 29.06.2024Published in 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) (29.06.2024)“…Recent commercial incarnations of processing-in-memory (PIM) maintain the standard DRAM interface and employ the all-bank mode execution to maximize bank-level…”
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HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE Inference
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…The Mixture of Experts (MoE) architecture has demonstrated significant advantages as it enables to increase the model capacity without a proportional increase…”
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NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing System
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Linear-response time-dependent Density Functional Theory (LR-TDDFT) is a widely used method for accurately predicting the excited-state properties of physical…”
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Seer: Predictive Runtime Kernel Selection for Irregular Problems
ISSN: 2643-2838Published: IEEE 02.03.2024Published in Proceedings / International Symposium on Code Generation and Optimization (02.03.2024)“…Modern GPUs are designed for regular problems and suffer from load imbalance when processing irregular data. Prior to our work, a domain expert selects the…”
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Accelerating Fourier and Number Theoretic Transforms using Tensor Cores and Warp Shuffles
Published: IEEE 01.09.2021Published in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“… To speed things up, fast Fourier transform (FFT) algorithms, which are reduced-complexity formulations for computing the DFT of a sequence, have been proposed and implemented for traditional processors and their corresponding instruction sets…”
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11
DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix Multiplication
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“…Numerous studies have proposed hardware architectures to accelerate sparse matrix multiplication, but these approaches often incur substantial area and power…”
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12
DARIS: An Oversubscribed Spatio-Temporal Scheduler for Real-Time DNN Inference on GPUs
Published: IEEE 22.06.2025Published in 2025 62nd ACM/IEEE Design Automation Conference (DAC) (22.06.2025)“… In particular, DARIS improves GPU utilization and uniquely analyzes GPU concurrency by oversubscribing computing resources…”
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13
Ultra Efficient Acceleration for De Novo Genome Assembly via Near-Memory Computing
Published: IEEE 01.09.2021Published in 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT) (01.09.2021)“…De novo assembly of genomes for which there is no reference, is essential for novel species discovery and metagenomics. In this work, we accelerate two key…”
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14
Gluon-Async: A Bulk-Asynchronous System for Distributed and Heterogeneous Graph Analytics
ISSN: 2641-7936Published: IEEE 01.09.2019Published in Proceedings / International Conference on Parallel Architectures and Compilation Techniques (01.09.2019)“…Distributed graph analytics systems for CPUs, like D-Galois and Gemini, and for GPUs, like D-IrGL and Lux, use a bulk-synchronous parallel (BSP…”
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15
OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration
Published: IEEE 09.07.2023Published in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)“… OpenDRC maintains hierarchical layouts with layer-wise bounding volume hierarchies and performs adaptive row-based partition to identify independent regions for check pruning and/or parallel processing…”
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16
TSUNAMI: A GPU Implementation of the WFA Algorithm
Published: IEEE 21.10.2023Published in 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT) (21.10.2023)“… TSUNAMI exploits GPU high-parallel computing to accelerate…”
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17
SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV
Published: IEEE 05.12.2021Published in 2021 58th ACM/IEEE Design Automation Conference (DAC) (05.12.2021)“… We evaluate SpV8 on Intel Xeon CPU and compare with multiple state-of-art SpMV algorithms using 71 sparse matrices…”
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18
Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping
ISSN: 1558-2434Published: Association on Computer Machinery 02.11.2020Published in Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (02.11.2020)“… In-memory computing can help address the memory-bandwidth bottleneck by minimizing data transfers…”
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EDGE: Event-Driven GPU Execution
ISSN: 2641-7936Published: IEEE 01.09.2019Published in Proceedings / International Conference on Parallel Architectures and Compilation Techniques (01.09.2019)“…GPUs are known to benefit structured applications with ample parallelism, such as deep learning in a datacenter. Recently, GPUs have shown promise for…”
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20
GPU Acceleration of RSA is Vulnerable to Side-channel Timing Attacks
ISSN: 1558-2434Published: ACM 01.11.2018Published in 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (01.11.2018)“… With the advent of general-purpose GPUs, the performance of RSA has been improved significantly by exploiting parallel computing on a GPU [9], [18], [23], [26…”
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