Search Results - 2D RISC array

A Distributed Shared Memory Model and C++ Templated Meta-Programming Interface for the Epiphany RISC Array Processor by Richie, David, Ross, James, Infantolino, Jamie

“…The Adapteva Epiphany many-core architecture comprises a scalable 2D mesh Network-on-Chip (NoC) of low-power…”
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Threaded MPI programming model for the Epiphany RISC array processor by Richie, David, Ross, James, Park, Song, Shires, Dale

“…•We investigate the use of MPI for programming the Epiphany RISC array processor…”
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Parallel programming model for the Epiphany many-core coprocessor using threaded MPI by Ross, James A., Richie, David A., Park, Song J., Shires, Dale R.

“…•We investigate the use of MPI for programming the Epiphany RISC array processor…”
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Implementing Hilbert transform for Digital Signal Processing on epiphany many-core coprocessor by Labowski, Kyle L., Ross, James A., Jungwirth, Patrick W., Richie, David A.

“…The Adapteva Epiphany MIMD architecture is a scalable 2D array of RISC cores with a fast network-on-chip (NoC…”
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Implementing OpenSHMEM for the Adapteva Epiphany RISC Array Processor by Ross, James A., Richie, David A.

“…The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC…”
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Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency by Perotti, Matteo, Riedel, Samuel, Cavalcante, Matheus, Benini, Luca

“… based on RISC-V's vector extension Zve64d. Using Spatz as the main Processing Element (PE…”
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Implementing OpenSHMEM for the Adapteva Epiphany RISC Array Processor by Ross, James A, Richie, David A

“…The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC…”
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OpenCL + OpenSHMEM Hybrid Programming Model for the Adapteva Epiphany Architecture by Richie, David, Ross, James

“… The Epiphany architecture comprises a 2D array of low-power RISC cores with minimal uncore functionality connected by a 2D mesh Network-on-Chip (NoC…”
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A Configurable 2D-Integer DCT Hardware Accelerator Compatible with H.266 Standard based on RISC-V Architecture by Nguyen, Nhu-Hoang, Dang, Tan-Phat, Tran, Tuan-Kiet, Bui, Thanh-Dat, Hoang, Trong-Thuc, Huynh, Huu-Thuan

“…This paper presents a system architecture for video compression, including a configurable 2D Discrete Cosine Transform (DCT…”
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Heterogeneous 3D Integration for a RISC-V System With STT-MRAM by Zhu, Lingjun, Bamberg, Lennart, Agnesina, Anthony, Catthoor, Francky, Milojevic, Dragomir, Komalan, Manu, Ryckaert, Julien, Garcia-Ortiz, Alberto, Lim, Sung Kyu

“… However, the process heterogeneity and the sophisticated back-end-of-line (BEOL) structure make it difficult to integrate the STT-MRAM in two-dimensional integrated circuits (2D ICs…”
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Systolic Array Matrix Multiplication Accelerator by Puscasu, Alexandru, Ciobanu, Catalin Bogdan, Buiu, Octavian

“… We designed a loosely-coupled matrix multiplier with a 2D systolic array. The accelerator is configured with matrices parameters…”
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CGRA-RISC: Simulation Infrastructure for Coupling CGRA Accelerator to RISC-V Processor by Ribeiro, Antonio Francisco Rente

“…), has potentiated alternative computing devices, commonly called accelerators.This set of devices includes the Coarse-Grained Reconfigurable Array (CGRA…”
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An OpenSHMEM Implementation for the Adapteva Epiphany Coprocessor by Ross, James, Richie, David

“… The Epiphany architecture exhibits massive many-core scalability with a physically compact 2D array of RISC CPU cores and a fast network-on-chip (NoC…”
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RISC Conversions for LNS Arithmetic in Embedded Systems by Drahoš, Peter, Kocúr, Michal, Haffner, Oto, Kučera, Erik, Kozáková, Alena

“…) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP…”
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Advances in Run-time Performance and Interoperability for the Adapteva Epiphany Coprocessor by Richie, David A., Ross, James A.

“…The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC…”
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CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration by Park, Sang-Soo, Chung, Ki-Seok

“… better matrix multiplications in terms of both speed and power consumption. Typically, accelerators with either a two-dimensional (2D…”
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Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference by Dupuis, Theo, Fournier, Yoan, AskariHemmat, MohammadHossein, Zarif, Nizar El, Leduc-Primeau, Francois, David, Jean Pierre, Savaria, Yvon

“… This processor is based on a modified version of Ara, an open-source 64-bit RISC-V "V" compliant processor…”
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Advances in Run-Time Performance and Interoperability for the Adapteva Epiphany Coprocessor by Richie, David A, Ross, James A

“…The energy-efficient Adapteva Epiphany architecture exhibits massive many-core scalability in a physically compact 2D array of RISC cores with a fast network-on-chip (NoC…”
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Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency by Cavalcante, Matheus, Perotti, Matteo, Riedel, Samuel, Benini, Luca

“…). Architecturally, the SCM is the Vector Register File (VRF) of Spatz, a compact 64-bit floating-point-capable vector processor based on RISC-V's Vector Extension Zve64d…”
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Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference by Dupuis, Théo, Fournier, Yoan, AskariHemmat, MohammadHossein, Nizar El Zarif, Leduc-Primeau, François, Jean Pierre David, Savaria, Yvon

“… This processor is based on a modified version of Ara, an open-source 64-bit RISC-V ``V'' compliant processor…”
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