Suchergebnisse - abstraction techniques for modeling and verification

Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held As Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25-30, 2020, Proceedings, Part I von Biere, Armin, Parker, David

“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems …”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held As Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25-30, 2020, Proceedings, Part II von Biere, Armin, Parker, David

“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems …”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25–30, 2020, Proceedings, Part I

“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems …”
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Tools and Algorithms for the Construction and Analysis of Systems: 26th International Conference, TACAS 2020, Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25–30, 2020, Proceedings, Part II

“… The papers are organized in topical sections as follows: Part I: Program verification; SAT and SMT; Timed and Dynamical Systems …”
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Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract von Mook, Niels, De Kock, Erwin, Arts, Bas, Chakraborty, Soham, Van Deursen, Arie

“… This paper proposes a modeling and analysis technique to verify SoC address maps …”
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A Formal Verification Method for the SOPC Software von Zhou, Shan, Wang, Jinbo, Jia, Jiao, Zhang, Chi, Wang, Ruixue

“… System on programmable chip (SOPC) is a kind of system on a programmable chip. The system architecture is superior to the traditional design pattern. The …”
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Verifying Controllers With Vision-Based Perception Using Safe Approximate Abstractions von Hsieh, Chiao, Li, Yangge, Sun, Dawei, Joshi, Keyur, Misailovic, Sasa, Mitra, Sayan

“… Fully formal verification of perception models is likely to remain challenging in the foreseeable future, and yet these models are being integrated into safety-critical control systems …”
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Possibilistic Cost Computation Tree Logic and Related Equivalence, Abstraction Technique von Deng, Hui, Zhang, Yuzhe, Huang, Zhilong

“… As the verification model, furthermore, we investigated the syntax and semantics of possibilistic cost computation tree logic and utilized them to develop verification characteristics …”
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Compositional Abstraction and Safety Synthesis Using Overlapping Symbolic Models von Meyer, Pierre-Jean, Girard, Antoine, Witrant, Emmanuel

“… In this paper, we develop a compositional approach to abstraction and safety synthesis for a general class of discrete-time nonlinear systems …”
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Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification von Gonzalez-de-Aledo, Pablo, Przigoda, Nils, Wille, Robert, Drechsler, Rolf, Sanchez, Pablo

“… UML and OCL are the de-facto specification languages for these tasks. They allow for capturing system properties and module behavior in an abstract but still formal fashion …”
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Automated verification and synthesis of stochastic hybrid systems: A survey von Lavaei, Abolfazl, Soudjani, Sadegh, Abate, Alessandro, Zamani, Majid

“… Stochastic hybrid systems have received significant attentions as a relevant modeling framework describing many systems, from engineering to the life sciences …”
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Specification and Verification Method of Parallel Hierarchical Timed Automata by Predicate Abstraction and Refinement von Yamane, Satoshi

“… The reduction technique of the state space for verifying embedded systems is crucial. On the other hand, Counterexample-Guided Abstraction Refinement (CEGAR …”
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Formal verification of a telerehabilitation system through an abstraction and refinement approach using Uppaal von Arfi, Farid, Courbis, Anne‐Lise, Lambolais, Thomas, Bughin, François, Hayot, Maurice

“… Formal methods are proven techniques that provide a rigorous mathematical basis to software development …”
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Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields von Pruss, Tim, Kalla, Priyank, Enescu, Florian

“… This paper introduces a technique to derive a word-level abstraction of the function implemented by a combinational logic circuit …”
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Superposition‐Based Abstractions for Quantum Data Encoding Verification von Govindankutty, Arun, Srinivasan, Sudarshan K.

“… The key idea to address scalability is the use of abstractions that reduce the verification problem to bit‐vector space …”
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Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification von Subramanyan, Pramod, Huang, Bo-Yuan, Vizel, Yakir, Gupta, Aarti, Malik, Sharad

“… A general technique for scalable system-level verification is to construct an abstraction of SoC hardware and verify firmware/software using …”
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Decomposing Software Verification into Off-the-Shelf Components: An Application to CEGAR von Beyer, Dirk, Haltermann, Jan, Lemberger, Thomas, Wehrheim, Heike

“… Techniques for software verification are typically realized as cohesive units of software with tightly coupled components …”
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Improving Formal Verification and Testing Techniques for Internet of Things and Smart Cities von Krichen, Moez

“… On the first hand the techniques realted to formal verification are as follows. First, Abstraction consists in modelling a part of the system accurately and the other parts at high level …”
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Scenario Description Language for Automated Driving Systems: A Two Level Abstraction Approach von Zhang, Xizhe, Khastgir, Siddartha, Jennings, Paul

“… Variety of scenario generation techniques have been advocated, including real-world data analysis, accident data analysis and via systems hazard analysis …”
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Set Partition and Trace Based Verification of Web Service Composition von Rai, Gopal N., Gangadharan, G.R.

“… Then, we propose a novel methodology for service interaction verification that uses service description (from WSDL …”
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