Suchergebnisse - Hardware Integrated circuits Reconfigurable logic and FPGAs Hardware accelerators

Interview – Design: ‘An FPGA Is A Reconfigurable Integrated Circuit Used To Implement Complex Logic Functions’

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Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems : Design of circuits and integrated systems von SILVA, M. L, FERREIRA, J. C

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US Patent Issued to EASY-LOGIC TECHNOLOGY on Aug. 9 for "Methods and apparatus for removing functional bugs and hardware trojans for integrated circuits implemented by field programmable gate array (FPGA)" (Chinese Inventors)

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Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration von Genc, Hasan, Kim, Seah, Amid, Alon, Haj-Ali, Ameer, Iyer, Vighnesh, Prakash, Pranav, Zhao, Jerry, Grubb, Daniel, Liew, Harrison, Mao, Howard, Ou, Albert, Schmidt, Colin, Steffl, Samuel, Wright, John, Stoica, Ion, Ragan-Kelley, Jonathan, Asanovic, Krste, Nikolic, Borivoje, Shao, Yakun Sophia

“… DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments …”
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Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology von Seshadri, Vivek, Lee, Donghyuk, Mullins, Thomas, Hassan, Hasan, Boroumand, Amirali, Kim, Jeremie, Kozuch, Michael A., Mutlu, Onur, Gibbons, Phillip B., Mowry, Todd C.

“… , CPU, GPU, FPGA, processing-in-memory). To overcome this bottleneck, we propose Ambit, an Accelerator-in-Memory for bulk bitwise operations …”
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GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic Algorithm von Kao, Sheng-Chun, Krishna, Tushar

“… DNN layers are multi-dimensional loops that can be ordered, tiled, and scheduled in myriad ways across space and time on DNN accelerators …”
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ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization von Guo, Cong, Zhang, Chen, Leng, Jingwen, Liu, Zihan, Yang, Fan, Liu, Yunxin, Guo, Minyi, Zhu, Yuhao

“… Even though this line of work brings algorithmic benefits, it also introduces significant hardware overheads due to variable-length encoding …”
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CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators von Boroumand, Amirali, Ghose, Saugata, Patel, Minesh, Hassan, Hasan, Lucia, Brandon, Ausavarungnirun, Rachata, Hsieh, Kevin, Hajinazar, Nastaran, Malladi, Krishna T., Zheng, Hongzhong, Mutlu, Onur

“… Specialized on-chip accelerators are widely used to improve the energy efficiency of computing systems …”
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Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design von Fan, Hongxiang, Chau, Thomas, Venieris, Stylianos I., Lee, Royson, Kouris, Alexandros, Luk, Wayne, Lane, Nicholas D., Abdelfattah, Mohamed S.

“… ) demands excessive computational and memory resources, which often compromises their hardware performance …”
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NAAS: Neural Accelerator Architecture Search von Lin, Yujun, Yang, Mengtian, Han, Song

“… Data-driven, automatic design space exploration of neural accelerator architecture is desirable for specialization and productivity …”
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Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks von Boroumand, Amirali, Ghose, Saugata, Akin, Berkin, Narayanaswami, Ravi, Oliveira, Geraldo F., Ma, Xiaoyu, Shiu, Eric, Mutlu, Onur

“… Emerging edge computing platforms often contain machine learning (ML) accelerators that can accelerate inference for a wide range of neural network (NN) models …”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks von Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“… In this paper we design and implement Caffeine, a hardware/software co-designed library to efficiently accelerate the entire CNN on FPGAs …”
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CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator von Sunny, Febin, Mirza, Asif, Nikdast, Mahdi, Pasricha, Sudeep

“… Domain-specific neural network accelerators have seen growing interest in recent years due to their improved energy efficiency and performance compared to CPUs and GPUs …”
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DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation von Hong, Seongmin, Moon, Seungjae, Kim, Junsoo, Lee, Sungjae, Kim, Minsub, Lee, Dongsoo, Kim, Joo-Young

“… to its sequential characteristic. Therefore, an efficient hardware platform is required to address the high …”
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PolySA: Polyhedral-Based Systolic Array Auto-Compilation von Cong, Jason, Wang, Jie

“… Automatic systolic array generation has long been an interesting topic due to the need to reduce the lengthy development cycles of manual designs. Existing …”
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Laconic Deep Learning Inference Acceleration von Sharify, Sayeh, Lascorz, Alberto Delmas, Mahmoud, Mostafa, Nikolic, Milos, Siu, Kevin, Stuart, Dylan Malone, Poulos, Zissis, Moshovos, Andreas

“… ). This method produces numerically identical results and does not affect overall accuracy. We present Laconic, a hardware accelerator that implements this approach to boost energy efficiency for inference with Deep Learning Networks …”
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DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA von Luo, Yukui, Gongye, Cheng, Fei, Yunsi, Xu, Xiaolin

“… ), such virtualization environments have posed many new security issues. This work investigates the integrity of DNN FPGA accelerators in clouds …”
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SODA: Stencil with Optimized Dataflow Architecture von Chi, Yuze, Cong, Jason, Wei, Peng, Zhou, Peipei

“… Such kernels are often offloaded to FPGAs to take advantages of the efficiency of dedicated hardware …”
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DSPlacer: DSP Placement for FPGA-based CNN Accelerator von Xie, Baohui, Zhu, Xinrui, Lu, Zhiyuan, Pu, Yuan, Wu, Tongkai, Zou, Xiaofeng, Yu, Bei, Chen, Tinghuan

“… Deploying convolutional neural networks (CNNs) on hardware platforms like Field Programmable Gate Arrays (FPGAs …”
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High-Performance FPGA-based Accelerator for Bayesian Neural Networks von Fan, Hongxiang, Ferianc, Martin, Rodrigues, Miguel, Zhou, Hongyu, Niu, Xinyu, Luk, Wayne

“… This work proposes a novel FPGA based hardware architecture to accelerate BNNs inferred through Monte Carlo Dropout …”
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