Suchergebnisse - Hardware Integrated circuits Reconfigurable logic and FPGAs

DSPlacer: DSP Placement for FPGA-based CNN Accelerator von Xie, Baohui, Zhu, Xinrui, Lu, Zhiyuan, Pu, Yuan, Wu, Tongkai, Zou, Xiaofeng, Yu, Bei, Chen, Tinghuan

“… Deploying convolutional neural networks (CNNs) on hardware platforms like Field Programmable Gate Arrays (FPGAs …”
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks von Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong

“… In this paper we design and implement Caffeine, a hardware/software co-designed library to efficiently accelerate the entire CNN on FPGAs …”
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Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration von Genc, Hasan, Kim, Seah, Amid, Alon, Haj-Ali, Ameer, Iyer, Vighnesh, Prakash, Pranav, Zhao, Jerry, Grubb, Daniel, Liew, Harrison, Mao, Howard, Ou, Albert, Schmidt, Colin, Steffl, Samuel, Wright, John, Stoica, Ion, Ragan-Kelley, Jonathan, Asanovic, Krste, Nikolic, Borivoje, Shao, Yakun Sophia

“… DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This …”
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SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture von Xia, Ke, Luo, Yukui, Xu, Xiaolin, Wei, Sheng

“… To fill the gap, we present SGX-FPGA, a trusted hardware isolation path enabling the first FPGA TEE by bridging SGX enclaves and FPGAs in the heterogeneous CPU-FPGA architecture …”
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FPGA-TrustZone: Security Extension of TrustZone to FPGA for SoC-FPGA Heterogeneous Architecture von Wang, Shupeng, Fan, Xindong, Xu, Xiao, Wang, Shuchen, Ju, Lei, Zhou, Zimeng

“… Experiments on real SoC-FPGA hardware development boards show that FPGA-TrustZone provides high security with low performance overhead …”
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BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices von Zhou, Zhe, Shi, Bizhao, Zhang, Zhe, Guan, Yijin, Sun, Guangyu, Luo, Guojie

“… platforms.To tackle this challenge, we propose BlockGNN, a software-hardware co-design approach to realize efficient GNN acceleration …”
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High-Performance FPGA-based Accelerator for Bayesian Neural Networks von Fan, Hongxiang, Ferianc, Martin, Rodrigues, Miguel, Zhou, Hongyu, Niu, Xinyu, Luk, Wayne

“… This work proposes a novel FPGA based hardware architecture to accelerate BNNs inferred through Monte Carlo Dropout …”
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An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren Scheme von Meng, Xiangchen, Tan, Yan, Jiang, Zijun, Lyu, Yangdi

“… Furthermore, we design specialized hardware …”
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Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAs von Chen, Yao, Yu, Feng, Wu, Di, Wong, Weng-Fai, He, Bingsheng

“… They have been used in many domains, such as networking, databases, and graph processing. Field-programmable gate arrays (FPGAs …”
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XShift: FPGA-efficient Binarized LLM with Joint Quantization and Sparsification von Zhou, Shuai, Tian, Huinan, Meng, Sisi, Chen, Jianli, Yu, Jun, Wang, Kun

“… a specialized inference framework. In response, we introduce XShift, an algorithm-hardware co-design framework optimized for efficient binarized LLM inference on FPGAs …”
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WSQ-AdderNet: Efficient Weight Standardization based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization von Zhang, Yunxiang, Sun, Biao, Jiang, Weixiong, Ha, Yajun, Hu, Miao, Zhao, Wenfeng

“… Recent proposals on hardware-optimal neural network architectures suggest that AdderNet with a lightweight ℓ …”
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DuoQ: A DSP Utilization-aware and Outlier-free Quantization for FPGA-based LLMs Acceleration von Yu, Zhuoquan, Ji, Huidong, Cao, Yue, Wu, Junfu, Yan, Xiaoze, Zheng, Lirong, Zou, Zhuo

“… To address this problem, we introduce DuoQ, an FPGA-oriented algorithm-hardware co-design framework …”
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April: Accuracy-Improved Floating-Point Approximation For Neural Network Accelerators von Chen, Yonghao, Zou, Jiaxiang, Chen, Xinyu

“… Floatingpoint approximation, such as Mitchell's logarithm, enables floating-point multiplication using simpler integer additions, thereby improving hardware efficiency …”
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An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA von Zhang, Chenming, Gong, Lei, Wang, Chao, Zhou, Xuehai

“… The reconfigurable platform offers possibilities for identifying the bitlevel unstructured redundancy during inference with different DNN models …”
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FLAG: An FPGA-Based System for Low-Latency GNN Inference Service Using Vector Quantization von Han, Yunki, Kim, Taehwan, Kim, Jiwan, Ha, Seohye, Kim, Lee-Sup

“… In this paper, we propose FLAG, an FPGA-based GNN inference serving system using vector quantization …”
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An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language Models von Hao, Yingbo, Chen, Huangxu, Zou, Yi, Yang, Yanfeng

“… However, deploying such a new format into existing hardware systems is still challenging, and the dominant solution for LLM inference at low precision is still low-bit quantization …”
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Classifying Computations on Multi-Tenant FPGAs von Gobulukoglu, Mustafa, Drewes, Colin, Hunter, William, Kastner, Ryan, Richmond, Dustin

“… Modern data centers leverage large FPGAs to provide low latency, high throughput, and low energy computation …”
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KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGA von Guo, Xiaorang, Bunarjyan, Tigran, Liu, Dai, Lienhard, Benjamin, Schulz, Martin

“… While current methods, including deep neural networks, enhance readout accuracy, they typically lack support for mid-circuit measurements essential for quantum error correction, and they usually rely …”
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CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics von Feng, Siying, Sun, Jiawen, Pal, Subhankar, He, Xin, Kaszyk, Kuba, Park, Dong-hyeon, Morton, Magnus, Mudge, Trevor, Cole, Murray, O'Boyle, Michael, Chakrabarti, Chaitali, Dreslinski, Ronald

“… reconfiguration as a synergistic solution to accelerate SpMV-based graph analytics algorithms. Building on previously proposed general-purpose reconfigurable hardware …”
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ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization von Guo, Cong, Zhang, Chen, Leng, Jingwen, Liu, Zihan, Yang, Fan, Liu, Yunxin, Guo, Minyi, Zhu, Yuhao

“… Even though this line of work brings algorithmic benefits, it also introduces significant hardware overheads due to variable-length encoding …”
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