Suchergebnisse - Algorithm/architecture co-design
-
1
Speed/Area-Efficient ECC Processor Implementation Over GF(2 ^m) on FPGA via Novel Algorithm-Architecture Co-Design
ISSN: 1063-8210, 1557-9999Veröffentlicht: New York IEEE 01.08.2023Veröffentlicht in IEEE transactions on very large scale integration (VLSI) systems (01.08.2023)“… ) has gradually become obsolete, leading to the implementation of PM with large field sizes. From this perspective, in this article, through a novel algorithm-architecture co …”
Volltext
Journal Article -
2
Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
ISSN: 1939-8018, 1939-8115Veröffentlicht: Boston Springer US 01.05.2011Veröffentlicht in Journal of signal processing systems (01.05.2011)“… The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL …”
Volltext
Journal Article -
3
Communication Algorithm-Architecture Co-Design for Distributed Deep Learning
ISSN: 2575-713XVeröffentlicht: IEEE 01.06.2021Veröffentlicht in Proceedings - International Symposium on Computer Architecture (01.06.2021)“… In this work, we identify the inefficiency in widely used all-reduce algorithms, and the opportunity of algorithm-architecture co-design …”
Volltext
Tagungsbericht -
4
High-Radix/Mixed-Radix NTT Multiplication Algorithm/Architecture Co-Design Over Fermat Modulus
ISSN: 0018-9340, 1557-9956Veröffentlicht: IEEE 01.10.2025Veröffentlicht in IEEE transactions on computers (01.10.2025)“… Polynomial multiplication using Number Theoretic Transform (NTT) is crucial in lattice-based post-quantum cryptography (PQC) and fully homomorphic encryption …”
Volltext
Journal Article -
5
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory
ISSN: 0278-0070, 1937-4151Veröffentlicht: New York IEEE 01.03.2024Veröffentlicht in IEEE transactions on computer-aided design of integrated circuits and systems (01.03.2024)“… algorithm/architecture co-design methodology that effectively doubles the equivalent data capacity …”
Volltext
Journal Article -
6
Invited: Accelerating Genome Analysis via Algorithm-Architecture Co-Design
Veröffentlicht: IEEE 09.07.2023Veröffentlicht in 2023 60th ACM/IEEE Design Automation Conference (DAC) (09.07.2023)“… To address these challenges, several algorithm-architecture co-design works have been proposed, targeting different steps of the genome analysis pipeline …”
Volltext
Tagungsbericht -
7
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization
ISSN: 1045-9219, 1558-2183Veröffentlicht: New York IEEE 01.08.2018Veröffentlicht in IEEE transactions on parallel and distributed systems (01.08.2018)“… In this paper, we present efficient realization of Householder Transform (HT) based QR factorization through algorithm-architecture co-design where we achieve performance …”
Volltext
Journal Article -
8
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design
ISSN: 0278-0070, 1937-4151Veröffentlicht: New York IEEE 01.02.2024Veröffentlicht in IEEE transactions on computer-aided design of integrated circuits and systems (01.02.2024)“… To tackle these challenges, this paper presents a computation-efficient training scheme for N:M sparse DNNs using algorithm, architecture, and dataflow co-design …”
Volltext
Journal Article -
9
Impala: Algorithm/Architecture Co-Design for In-Memory Multi-Stride Pattern Matching
ISSN: 2378-203XVeröffentlicht: IEEE 01.02.2020Veröffentlicht in Proceedings - International Symposium on High-Performance Computer Architecture (01.02.2020)“… High-throughput and concurrent processing of thousands of patterns on each byte of an input stream is critical for many applications with real-time processing …”
Volltext
Tagungsbericht -
10
An Algorithm Architecture Co-Design for CMOS Compressive High Dynamic Range Imaging
ISSN: 2573-0436, 2333-9403, 2333-9403Veröffentlicht: Piscataway IEEE 01.09.2016Veröffentlicht in IEEE transactions on computational imaging (01.09.2016)“… Standard image sensors feature dynamic range about 60 to 70 dB while the light flux of natural scenes may be over 120 dB. Most imagers dedicated to address …”
Volltext
Journal Article -
11
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design
ISSN: 2380-6923Veröffentlicht: IEEE 01.01.2019Veröffentlicht in VLSI design (01.01.2019)“… ). In this paper, we present a systematic methodology of algorithm-architecture co-design to accelerate matrix-vector operations where we emphasize on the matrix-vector multiplication (gemv …”
Volltext
Tagungsbericht -
12
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
ISSN: 2378-203XVeröffentlicht: IEEE 01.02.2021Veröffentlicht in Proceedings - International Symposium on High-Performance Computer Architecture (01.02.2021)“… In this paper, we present SpAtten, an efficient algorithm-architecture co-design that leverages token sparsity, head sparsity, and quantization opportunities to reduce the attention computation and memory access …”
Volltext
Tagungsbericht -
13
Accelerating LLM Inference via Low-Bit Fine-Grained Quantization Algorithm and Bit-Level Accelerator Co-Design
ISSN: 0018-9340, 1557-9956Veröffentlicht: IEEE 2025Veröffentlicht in IEEE transactions on computers (2025)“… In this paper, we present a comprehensive solution to improve LLM inference performance under ultra-low weight precision, meticulously optimized through algorithm and architecture co-design …”
Volltext
Journal Article -
14
Ultra Low Power Sensor Node for Security Applications, Facilitated by Algorithm-Architecture Co-design
ISSN: 2380-6923Veröffentlicht: IEEE 01.01.2017Veröffentlicht in VLSI design (01.01.2017)“… Design of an ultra-low power sensor node for identifying human trespassing is proposed, that can be attractive for security applications. Approximate Frequency …”
Volltext
Tagungsbericht -
15
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity
ISSN: 0278-0070, 1937-4151Veröffentlicht: IEEE 2025Veröffentlicht in IEEE transactions on computer-aided design of integrated circuits and systems (2025)“… To overcome these limitations, we present Dyadic Block PIM (DB-PIM), a groundbreaking algorithm-architecture co-design framework to harness both value-level and bit-level sparsity …”
Volltext
Journal Article -
16
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation
ISSN: 2380-6923Veröffentlicht: IEEE 01.01.2016Veröffentlicht in 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) (01.01.2016)“… Finally, we show that algorithm-architecture co-design leads to the most efficient realization of HT …”
Volltext
Tagungsbericht Journal Article -
17
Algorithm/Architecture Co-Design of 3-D Spatio-Temporal Motion Estimation for Video Coding
ISSN: 1520-9210, 1941-0077Veröffentlicht: New York, NY IEEE 01.04.2007Veröffentlicht in IEEE transactions on multimedia (01.04.2007)“… This paper presents a new spatio-temporal motion estimation algorithm and its VLSI architecture for video coding based on algorithm and architecture co-design methodology …”
Volltext
Journal Article -
18
ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse
Veröffentlicht: IEEE 01.10.2022Veröffentlicht in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) (01.10.2022)“… ARK enables practical FHE workloads with a novel algorithm-architecture co-design to accelerate …”
Volltext
Tagungsbericht -
19
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture
ISSN: 0018-9340, 1557-9956Veröffentlicht: New York IEEE 01.10.2022Veröffentlicht in IEEE transactions on computers (01.10.2022)“… ) architecture through an algorithm-architecture co-optimization manner. To enable the efficient in-memory implementations, we come up to reformulate TC with bitwise logic operations (such as AND …”
Volltext
Journal Article -
20
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture
ISSN: 0278-0070, 1937-4151Veröffentlicht: New York IEEE 01.02.2023Veröffentlicht in IEEE transactions on computer-aided design of integrated circuits and systems (01.02.2023)“… To tackle this issue, we present an algorithm-architecture co-design named DTATrans. We find empirically that the tolerance to the noise varies from token to token in attention-based NLP models …”
Volltext
Journal Article