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DPTC - An FPGA-Based Trace Compression

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Titel: DPTC - An FPGA-Based Trace Compression
Autoren: Bruni, Giovanni, 1989, Johansson, Håkan T, 1977
Quelle: IEEE Transactions on Circuits and Systems I: Regular Papers. 67(1):189-197
Schlagwörter: data compression, Analog-to-digital conversion (ADC), Central Processing Unit, data acquisition, VHDL, Data compression, Detectors, real-time data acquisition, Bandwidth, lossless compression, open source, Field programmable gate arrays, variable-length code, front-end electronics, field programmable gate array (FPGA), Encoding
Beschreibung: Recording of flash-ADC traces is challenging from both the transmission bandwidth and storage cost perspectives. This work presents a configuration-free lossless compression algorithm, which addresses both limitations, by compressing the data on-the-fly in the controlling FPGA. Thus it can easily be used directly in front-end electronics. The method first computes the differences between consecutive samples in the traces, thereby concentrating the most probable values around zero. The values are then stored as groups of four, with only the necessary least-significant bits in a variable-length code, packed in a stream of 32-bit words. To evaluate the efficiency, the storage cost of compressed traces is modeled as a baseline cost including ADC noise, and a cost for pulses that depends on amplitude and width. The free parameters and the validity of the model are determined by compressing artificial traces with varying characteristics. The compression method was also applied to actual data from different types of detectors. A typical storage cost is around 4 to 5 bits per sample. Code for the FPGA implementation in VHDL and for the CPU decompression routine in C are available as open source software, both able to operate at speeds of 400 Msamples/s.
Dateibeschreibung: electronic
Zugangs-URL: https://research.chalmers.se/publication/515151
https://research.chalmers.se/publication/515247
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  Data: DPTC - An FPGA-Based Trace Compression
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  Data: <searchLink fieldCode="AR" term="%22Bruni%2C+Giovanni%22">Bruni, Giovanni</searchLink>, 1989<br /><searchLink fieldCode="AR" term="%22Johansson%2C+Håkan+T%22">Johansson, Håkan T</searchLink>, 1977
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  Data: <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i>. 67(1):189-197
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  Data: <searchLink fieldCode="DE" term="%22data+compression%22">data compression</searchLink><br /><searchLink fieldCode="DE" term="%22Analog-to-digital+conversion+%28ADC%29%22">Analog-to-digital conversion (ADC)</searchLink><br /><searchLink fieldCode="DE" term="%22Central+Processing+Unit%22">Central Processing Unit</searchLink><br /><searchLink fieldCode="DE" term="%22data+acquisition%22">data acquisition</searchLink><br /><searchLink fieldCode="DE" term="%22VHDL%22">VHDL</searchLink><br /><searchLink fieldCode="DE" term="%22Data+compression%22">Data compression</searchLink><br /><searchLink fieldCode="DE" term="%22Detectors%22">Detectors</searchLink><br /><searchLink fieldCode="DE" term="%22real-time+data+acquisition%22">real-time data acquisition</searchLink><br /><searchLink fieldCode="DE" term="%22Bandwidth%22">Bandwidth</searchLink><br /><searchLink fieldCode="DE" term="%22lossless+compression%22">lossless compression</searchLink><br /><searchLink fieldCode="DE" term="%22open+source%22">open source</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22variable-length+code%22">variable-length code</searchLink><br /><searchLink fieldCode="DE" term="%22front-end+electronics%22">front-end electronics</searchLink><br /><searchLink fieldCode="DE" term="%22field+programmable+gate+array+%28FPGA%29%22">field programmable gate array (FPGA)</searchLink><br /><searchLink fieldCode="DE" term="%22Encoding%22">Encoding</searchLink>
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  Label: Description
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  Data: Recording of flash-ADC traces is challenging from both the transmission bandwidth and storage cost perspectives. This work presents a configuration-free lossless compression algorithm, which addresses both limitations, by compressing the data on-the-fly in the controlling FPGA. Thus it can easily be used directly in front-end electronics. The method first computes the differences between consecutive samples in the traces, thereby concentrating the most probable values around zero. The values are then stored as groups of four, with only the necessary least-significant bits in a variable-length code, packed in a stream of 32-bit words. To evaluate the efficiency, the storage cost of compressed traces is modeled as a baseline cost including ADC noise, and a cost for pulses that depends on amplitude and width. The free parameters and the validity of the model are determined by compressing artificial traces with varying characteristics. The compression method was also applied to actual data from different types of detectors. A typical storage cost is around 4 to 5 bits per sample. Code for the FPGA implementation in VHDL and for the CPU decompression routine in C are available as open source software, both able to operate at speeds of 400 Msamples/s.
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        Value: 10.1109/TCSI.2019.2945179
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      – SubjectFull: Analog-to-digital conversion (ADC)
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      – SubjectFull: front-end electronics
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      – SubjectFull: field programmable gate array (FPGA)
        Type: general
      – SubjectFull: Encoding
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      – TitleFull: DPTC - An FPGA-Based Trace Compression
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            NameFull: Johansson, Håkan T
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