Efficient Parallel Architectures for Future Radar Signal Processing
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| Název: | Efficient Parallel Architectures for Future Radar Signal Processing |
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| Autoři: | Åhlander, Anders |
| Témata: | radar signal processing, space-time adaptive processing, Keywords: computer architecture |
| Popis: | The processing demands on future embedded radar signal processors may stretch to severaltrillions of floating-point operations per second (TFLOPS). This is an increase of two to threeorders of magnitude relative to the requirements of today. Still, the tight size and powerconstraints are unchanged. To meet this, new, highly parallel computer systems are needed. Thesystems should efficiently deliver very high performance, as well as being general enough.Another challenge for future signal processors is the requirement for having huge workingmemories that are accessed in complicated patterns.This thesis analyses the challenges of two classes of radar signal processing applications,namely Space-Time Adaptive Processing (STAP), which represents performance-intensiveapplications, and Synthetic Aperture Radar (SAR) processing, which represents memoryintensiveapplications. In addition to the actual performance and memory aspects of theapplications, the desire for low-effort application development and maintenance is taken intoconsideration.A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives acombination of the high computational density in the SIMD processing modules with the overallflexibility provided on the system level. An embedded signal processing system based on thearchitecture is shown to be capable of TFLOPS class performance using standard CMOS VLSItechnology available in the year 2001. The system is, for the given application domain,considered to have the same generality as commercial off-the-shelf (COTS) hardware, but hasseveral years of time lead over COTS with regard to the computational performance.The studied SAR processing is characterized by operating on huge data sets and having varying,non-linear data access paths. For this, algorithm solutions and execution schemes in interplaywith a system parallelization approach are proposed. It is shown that it is possible to obtainefficient memory accesses, despite the complicated memory access patterns. It is also shownthat the computational burden from complex interpolation kernels can be reduced throughextensive calculation reuse.Efficient engineering of complex applications in this context is discussed. The use of semitransparent,platform-based development is demonstrated for STAP and SAR, and advocated forobtaining high engineering efficiency and long system sustainability, as well as highperformance efficiency.The overall conclusion drawn from this work is that a solid knowledge of the applicationdomain and its future requirements, in combination with an understanding of its interaction withcomputational architectures, potentially enables several years of lead time in the realization ofnew, advanced signal processing products. The important requirements on programmability andsustainability must also be taken into account in order to achieve a viable signal processingsolution. |
| Přístupová URL adresa: | https://research.chalmers.se/publication/41284 |
| Databáze: | SwePub |
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| Items | – Name: Title Label: Title Group: Ti Data: Efficient Parallel Architectures for Future Radar Signal Processing – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Åhlander%2C+Anders%22">Åhlander, Anders</searchLink> – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22radar+signal+processing%22">radar signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22space-time+adaptive+processing%22">space-time adaptive processing</searchLink><br /><searchLink fieldCode="DE" term="%22Keywords%3A+computer+architecture%22">Keywords: computer architecture</searchLink> – Name: Abstract Label: Description Group: Ab Data: The processing demands on future embedded radar signal processors may stretch to severaltrillions of floating-point operations per second (TFLOPS). This is an increase of two to threeorders of magnitude relative to the requirements of today. Still, the tight size and powerconstraints are unchanged. To meet this, new, highly parallel computer systems are needed. Thesystems should efficiently deliver very high performance, as well as being general enough.Another challenge for future signal processors is the requirement for having huge workingmemories that are accessed in complicated patterns.This thesis analyses the challenges of two classes of radar signal processing applications,namely Space-Time Adaptive Processing (STAP), which represents performance-intensiveapplications, and Synthetic Aperture Radar (SAR) processing, which represents memoryintensiveapplications. In addition to the actual performance and memory aspects of theapplications, the desire for low-effort application development and maintenance is taken intoconsideration.A multiple SIMD architecture is proposed for the STAP calculations. This architecture gives acombination of the high computational density in the SIMD processing modules with the overallflexibility provided on the system level. An embedded signal processing system based on thearchitecture is shown to be capable of TFLOPS class performance using standard CMOS VLSItechnology available in the year 2001. The system is, for the given application domain,considered to have the same generality as commercial off-the-shelf (COTS) hardware, but hasseveral years of time lead over COTS with regard to the computational performance.The studied SAR processing is characterized by operating on huge data sets and having varying,non-linear data access paths. For this, algorithm solutions and execution schemes in interplaywith a system parallelization approach are proposed. It is shown that it is possible to obtainefficient memory accesses, despite the complicated memory access patterns. It is also shownthat the computational burden from complex interpolation kernels can be reduced throughextensive calculation reuse.Efficient engineering of complex applications in this context is discussed. The use of semitransparent,platform-based development is demonstrated for STAP and SAR, and advocated forobtaining high engineering efficiency and long system sustainability, as well as highperformance efficiency.The overall conclusion drawn from this work is that a solid knowledge of the applicationdomain and its future requirements, in combination with an understanding of its interaction withcomputational architectures, potentially enables several years of lead time in the realization ofnew, advanced signal processing products. The important requirements on programmability andsustainability must also be taken into account in order to achieve a viable signal processingsolution. – Name: URL Label: Access URL Group: URL Data: <link linkTarget="URL" linkTerm="https://research.chalmers.se/publication/41284" linkWindow="_blank">https://research.chalmers.se/publication/41284</link> |
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| RecordInfo | BibRecord: BibEntity: Languages: – Text: English Subjects: – SubjectFull: radar signal processing Type: general – SubjectFull: space-time adaptive processing Type: general – SubjectFull: Keywords: computer architecture Type: general Titles: – TitleFull: Efficient Parallel Architectures for Future Radar Signal Processing Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Åhlander, Anders IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 2007 Identifiers: – Type: isbn-print Value: 9172919345 – Type: isbn-print Value: 9789172919341 – Type: issn-locals Value: CTH_SWEPUB |
| ResultId | 1 |