Code Generation for a SIMD Architecture with Custom Memory Organisation
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| Title: | Code Generation for a SIMD Architecture with Custom Memory Organisation |
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| Authors: | Arslan, Mehmet Ali, Gruian, Flavius, Kuchcinski, Krzysztof, Karlsson, Andreas |
| Contributors: | Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator, Lund University, Profile areas and other strong research environments, Strategic research areas (SRA), ELLIIT: the Linköping-Lund initiative on IT and mobile communication, Lunds universitet, Profilområden och andra starka forskningsmiljöer, Strategiska forskningsområden (SFO), ELLIIT: the Linköping-Lund initiative on IT and mobile communication, Originator, Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator |
| Source: | 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP) Conference on Design & Architectures for Signal & Image Processing (DASIP 2016). :90-97 |
| Subject Terms: | Engineering and Technology, Electrical Engineering, Electronic Engineering, Information Engineering, Embedded Systems, Teknik, Elektroteknik och elektronik, Inbäddad systemteknik, Natural Sciences, Computer and Information Sciences, Computer Sciences, Naturvetenskap, Data- och informationsvetenskap (Datateknik), Datavetenskap (Datalogi) |
| Description: | Today’s multimedia and DSP applications impose requirements on performance and power consumption that only custom processor architectures with SIMD capabilities can satisfy. However, the specific features of such architectures, including vector operations and high-bandwidth complex memory organization, make them notoriously complicated and time consuming to program. In this paper we present an automated code generation approach that dramatically reduces the effort of programming such architectures, by carrying out instruction scheduling and memory allocation based on a constraint programming formulation. Furthermore, the quality of the generated code is close to that of hand-written code by an experienced programmer with knowledge of the architecture. We demonstrate the viability of our approach on an existing custom heterogeneous DSP architecture, by compiling and running a number of typical DSP kernels, and comparing the results to hand-optimized code. |
| Database: | SwePub |
Nájsť tento článok vo Web of Science | Abstract: | Today’s multimedia and DSP applications impose requirements on performance and power consumption that only custom processor architectures with SIMD capabilities can satisfy. However, the specific features of such architectures, including vector operations and high-bandwidth complex memory organization, make them notoriously complicated and time consuming to program. In this paper we present an automated code generation approach that dramatically reduces the effort of programming such architectures, by carrying out instruction scheduling and memory allocation based on a constraint programming formulation. Furthermore, the quality of the generated code is close to that of hand-written code by an experienced programmer with knowledge of the architecture. We demonstrate the viability of our approach on an existing custom heterogeneous DSP architecture, by compiling and running a number of typical DSP kernels, and comparing the results to hand-optimized code. |
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| DOI: | 10.1109/DASIP.2016.7853802 |