VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture - Gruian, Flavius; Westmijze, Mark; Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Parallel Systems, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Parallella System, Originator; Lund University, Faculty of Engineering, LTH, Departments at LTH, Department of Computer Science, Lunds universitet, Lunds Tekniska Högskola, Institutioner vid LTH, Institutionen för datavetenskap, Originator (Proceedings of the 23rd Annual Acm Symposium on Applied Computing Symposium on Applied Computing (SAC), 2008)