Memory array and methods used in forming a memory array
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| Title: | Memory array and methods used in forming a memory array |
|---|---|
| Patent Number: | 12274,056 |
| Publication Date: | April 08, 2025 |
| Appl. No: | 18/433863 |
| Application Filed: | February 06, 2024 |
| Abstract: | A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed. |
| Inventors: | Micron Technology, Inc. (Boise, ID, US) |
| Assignees: | Micron Technology, Inc. (Boise, ID, US) |
| Claim: | 1. A memory array, comprising: a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a first select gate tier above the insulator etch-stop tier, a second select gate tier above the first select gate tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the second select gate tier, the first select gate tier comprising a conductively-doped semiconductive material, the second select gate tier comprising a conducting metal material; an insulating material vertically between and vertically separating the conducting metal material of the second select gate tier and the conductively-doped semiconductive material of the first select gate tier, the conducting metal material in the second select gate tier and the conductively-doped semiconductive material in the first select gate tier being directly electrically coupled to one another through leaks through the insulative material; a channel opening extending through the insulative tiers, the wordline tiers, the first and second select gate tiers, and the insulator etch-stop tier, the channel opening having a base surface on the conductive tier; a charge-blocking material in the channel opening, the charge-blocking material extending continuously along the insulative tiers, the wordline tiers, the first and second select gate tiers, and the insulator etch-stop tier to directly contact the upper surface of the conductive tier; and a channel material in the channel opening extending elevationally along the insulative tiers, the wordline tiers, and the first and second select gate tiers and being in direct physical contact with the upper surface and directly electrically coupled with the conductive material in the conductive tier. |
| Claim: | 2. The memory array of claim 1 wherein the insulator etch-stop tier comprises silicon dioxide. |
| Claim: | 3. The memory array of claim 1 wherein the insulator etch-stop tier comprises silicon nitride. |
| Claim: | 4. The memory array of claim 1 wherein the insulator etch-stop tier comprises an insulative metal oxide comprising multiple different metal elements. |
| Claim: | 5. The memory array of claim 1 wherein the insulator etch-stop tier is vertically thinner than the first select gate tier. |
| Claim: | 6. The memory array of claim 1 wherein the insulator etch-stop tier is vertically thinner than each of the insulative tiers and the wordline tiers. |
| Claim: | 7. A memory array comprising: a vertical stack comprising: a conductive tier; an insulator tier above the conductive tier; a first stack comprising multiple select gate tiers above the insulator tier, a first of the select gate tiers comprising select gate conducting material comprising elemental W and comprising at least one of Al 2 O 3 and HfO x , a second of the select gate tiers comprising select gate conductor material, the select gate conductor material being vertically thicker than the select gate conducting material; and a second stack comprising vertically-alternating insulative tiers and wordline tiers above the first stack, the wordline tiers comprising gate regions of individual memory cells, individual of the gate regions comprising part of a wordline in individual of the wordline tiers; a channel material structure extending elevationally continuously through the insulative tiers, the wordline tiers, the first select gate tier, and the second select gate tier, the channel material being directly electrically coupled with conductive material in the conductive tier; each of the individual memory cells comprising a memory structure between the individual gate regions and the channel material; the memory structure comprising a charge-blocking region laterally inward of the individual gate regions, a storage region laterally inward of individual of the charge-blocking regions, and insulative charge-passage material laterally inward of individual of the storage regions, the charge-blocking regions extending continuously along the wordline tiers, along the select gate tiers, and along the insulator tier, and directly contacting the upper surface of the conductive tier; and a select gate in the first select gate tier and in the second select gate tier, the select gate comprising the select gate conducting material in the first select gate tier and the select gate conductor material in the second select gate tier. |
| Claim: | 8. The memory array of claim 7 comprising horizontally-elongated insulator structures extending elevationally through the insulative tiers and the wordline tiers, the horizontally-elongated insulator structures laterally separating individual wordlines in individual of the wordline tiers. |
| Claim: | 9. The memory array of claim 7 comprising NAND. |
| Claim: | 10. The memory array of claim 9 comprising CMOS under array circuitry electrically coupled to at least one of the conductive tier, the select gate tier, and the wordlines. |
| Patent References Cited: | 9741737 August 2017 Huang et al. 10014309 July 2018 Dorhout et al. 10734403 August 2020 Eom et al. 11937423 March 2024 Tran 2009/0101960 April 2009 Aoki et al. 2011/0121403 May 2011 Lee 2011/0287612 November 2011 Lee et al. 2012/0058629 March 2012 You et al. 2013/0146980 June 2013 Tanzawa 2013/0148400 June 2013 Murooka 2014/0264360 September 2014 Huang et al. 2014/0291747 October 2014 Simsek-Ege 2015/0140753 May 2015 Simsek-Ege et al. 2016/0099323 April 2016 Hopkins 2017/0117049 April 2017 Rajwade 2017/0148809 May 2017 Nishikawa et al. 2018/0090373 March 2018 Sharangpani et al. 2018/0366386 December 2018 Petz 2019/0295956 September 2019 Kawai 2020/0111808 April 2020 Liu et al. 2020/0266146 August 2020 Nishida 107706190 February 2018 202010125017.5 December 2022 |
| Primary Examiner: | Ashbahian, Eric K |
| Attorney, Agent or Firm: | Wells St. John P.S. |
| Accession Number: | edspgr.12274056 |
| Database: | USPTO Patent Grants |
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