Thread serialization, distributed parallel programming, and runtime extensions of parallel computing platform
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| Title: | Thread serialization, distributed parallel programming, and runtime extensions of parallel computing platform |
|---|---|
| Patent Number: | 11257,180 |
| Publication Date: | February 22, 2022 |
| Appl. No: | 16/929790 |
| Application Filed: | July 15, 2020 |
| Abstract: | Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment. |
| Inventors: | Intel Corporation (Santa Clara, CA, US) |
| Assignees: | Intel Corporation (Santa Clara, CA, US) |
| Claim: | 1. A semiconductor package apparatus, comprising: a substrate; and a host graphics processor operatively coupled to the substrate, the host graphics processor including logic that is at least partially implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic to: detect, in a runtime environment, a graphic application for use in a parallel computing platform by detecting active execution lanes of the graphic application, wherein detecting active execution lanes comprises utilizing a predetermined value; and modify, during runtime and in response to detecting the graphic application, source code in connection with the parallel computing platform by adding at least one source code extension that is to execute a loop body once for each unique value that different threads in a warp hold as the predetermined value. |
| Claim: | 2. The semiconductor package apparatus of claim 1 , wherein: for each loop iteration, execution lanes whose value matches the predetermined value are active; and for each loop iteration, execution lanes whose value does not match the predetermined value are inactive. |
| Claim: | 3. The semiconductor package apparatus of claim 2 , wherein modifying the source code comprises executing a loop body once for each detected active execution lane. |
| Claim: | 4. The semiconductor package apparatus of claim 1 , wherein the at least one source code extension includes an iteration construct that is to iterate over elements of a varying predetermined variable, and process subsets of the elements that share a same value. |
| Claim: | 5. The semiconductor package apparatus of claim 1 , wherein the at least one source code extension includes an iteration construct that is to perform reduction across all lanes in the warp by adding values of a given value in each detected active execution lane. |
| Claim: | 6. A graphics processing system, comprising: a memory; and a semiconductor package apparatus operatively coupled to the memory, the semiconductor package apparatus including a substrate and a host graphics processor operatively coupled to the substrate, wherein the host graphics processor includes logic to: detect, in a runtime environment, a graphic application for use in a parallel computing platform by detecting active execution lanes of the graphic application, wherein detecting active execution lanes comprises utilizing a predetermined value; and modify, during runtime and in response to detecting the graphic application, source code in connection with the parallel computing platform by adding at least one source code extension that is to execute a loop body once for each unique value that different threads in a warp hold as the predetermined value. |
| Claim: | 7. The graphics processing system of claim 6 , wherein: for each loop iteration, execution lanes whose value matches the predetermined value are active; and for each loop iteration, execution lanes whose value does not match the predetermined value are inactive. |
| Claim: | 8. The graphics processing system of claim 7 , wherein modifying the source code comprises executing a loop body once for each detected active execution lane. |
| Claim: | 9. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a host graphics processor, cause the host graphics processor to: detect, in a runtime environment, a graphic application for use in a parallel computing platform by detecting active execution lanes of the graphic application, wherein detecting active execution lanes comprises utilizing a predetermined value; and modify, during runtime and in response to detecting the graphic application, source code in connection with the parallel computing platform by adding at least one source code extension that is to execute a loop body once for each unique value that different threads in a warp hold as the predetermined value. |
| Claim: | 10. The at least one non-transitory computer readable medium of claim 9 , wherein: for each loop iteration, execution lanes whose value matches the predetermined value are active; and for each loop iteration, execution lanes whose value does not match the predetermined value are inactive. |
| Claim: | 11. The at least one non-transitory computer readable medium of claim 10 , wherein modifying the source code comprises executing a loop body once for each detected active execution lane. |
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| Primary Examiner: | Nguyen, Phong X |
| Attorney, Agent or Firm: | Jordan IP Law, LLC |
| Accession Number: | edspgr.11257180 |
| Database: | USPTO Patent Grants |
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