Soft-aided decoding of staircase codes
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| Název: | Soft-aided decoding of staircase codes |
|---|---|
| Patent Number: | 11251,809 |
| Datum vydání: | February 15, 2022 |
| Appl. No: | 15/734544 |
| Application Filed: | July 09, 2019 |
| Abstrakt: | A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a decoder to produce decoded bits using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. The marked reliable and unreliable bits are computed by calculation and marking blocks based on an absolute value of log-likelihood ratios of the HD-FEC coded signal. The HD-FEC coded signal may be, for example, a staircase code coded signal or a product code coded signal. |
| Inventors: | Technische Universiteit Eindhoven (Eindhoven, NL) |
| Assignees: | Technische Universiteit Eindhoven (Eindhoven, NL) |
| Claim: | 1. A method for decoding a hard-decision (HD) forward error correcting (FEC) coded signal received by a device over a communication channel, the method comprising: decoding the HD-FEC coded signal by the device to produce decoded bits; wherein the decoding uses marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal. |
| Claim: | 2. The method of claim 1 , wherein the decoding comprises: estimating code bits from the coded signal by an HD-based demapper; and generating the decoded bits from the estimated code bits by an HD-FEC decoder. |
| Claim: | 3. The method of claim 1 , wherein the decoding comprises: computing the marked bits based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. |
| Claim: | 4. The method of claim 1 , wherein the decoding comprises: marking a bit of the HD-FEC coded signal as a reliable bit whenever an absolute value of a log-likelihood ratio for the bit exceeds a predetermined threshold δ. |
| Claim: | 5. The method of claim 4 , wherein δ=10, or δ=11, or δ=12. |
| Claim: | 6. The method of claim 1 , wherein the decoding comprises: sorting bits of the HD-FEC coded signal by the log-likelihood ratios for the bits and marking a subset of the sorted bits having lowest log-likelihood ratios as unreliable bits. |
| Claim: | 7. The method of claim 1 , wherein the communication channel is optical, wired, or wireless. |
| Claim: | 8. The method of claim 1 , wherein the hard-decision (HD) forward error correcting (FEC) coded signal is a staircase code (SCC) coded signal, a product code (PC) coded signal, a Hamming code coded signal, a BCH code coded signal, or a Reed-Solomon code coded signal. |
| Claim: | 9. The method of claim 1 , wherein the decoding comprises detecting miscorrections and flipping bits whenever a miscorrection is detected. |
| Claim: | 10. A device for decoding a hard-decision (HD) forward error correcting (FEC) coded signal received by the device, the device comprising: a bit-marking circuit adapted to produce marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal; an HD-FEC decoder adapted to decode the HD-FEC coded signal received by the device to produce decoded bits; wherein the HD-FEC decoder uses the marked reliable bits and the marked unreliable bits. |
| Claim: | 11. The device of claim 10 , wherein the HD-FEC decoder comprises an HD-based demapper adapted to estimate code bits from the coded signal; and a bounded distance decoder (BDD) adapted to decode the decoded bits from the estimated code bits using the marked reliable bits and the marked unreliable bits. |
| Claim: | 12. The device of claim 10 , wherein the bit-marking circuit is adapted to compute the marked reliable bits and the marked unreliable bits based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. |
| Claim: | 13. The device of claim 10 , wherein the bit-marking circuit is adapted to mark a bit of the HD-FEC coded signal as a reliable bit whenever an absolute value of a log-likelihood ratio for the bit exceeds a predetermined threshold δ. |
| Claim: | 14. The device of claim 13 , wherein δ=10, or δ=11, or δ=12. |
| Claim: | 15. The device of claim 10 , wherein the bit marking circuit is adapted to sort bits of the HD-FEC coded signal by the log-likelihood ratios of the bits and to mark a subset of the sorted bits having lowest log-likelihood ratios as unreliable bits. |
| Claim: | 16. A system for communicating a hard-decision (HD) forward error correcting (FEC) coded signal, the device comprising: a transmitter adapted to transmit the hard-decision (HD) forward error correcting (FEC) coded signal; a receiver adapted to receive the hard-decision (HD) forward error correcting (FEC) coded signal; wherein the receiver comprises: a bit-marking circuit adapted to produce marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal; an HD-FEC decoder adapted to decode the HD-FEC coded signal received by the device to produce decoded bits; wherein the decoder uses the marked reliable bits and the marked unreliable bits. |
| Claim: | 17. The system of claim 16 , wherein the HD-FEC decoder comprises an HD-based demapper adapted to estimate code bits from the coded signal; and a bounded distance decoder (BDD) adapted to decode the decoded bits from the estimated code bits using the marked reliable bits and the marked unreliable bits. |
| Claim: | 18. The system of claim 16 , wherein the bit-marking circuit is adapted to compute the marked reliable bits and the marked unreliable bits based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. |
| Claim: | 19. The system of claim 16 , wherein the bit-marking circuit is adapted to mark a bit of the HD-FEC coded signal as a reliable bit whenever an absolute value of a log-likelihood ratio for the bit exceeds a predetermined threshold δ. |
| Claim: | 20. The system of claim 16 , wherein the bit marking circuit is adapted to sort bits of the HD-FEC coded signal by the log-likelihood ratios of the bits and to mark a subset of the sorted bits having lowest log-likelihood ratios as unreliable bits. |
| Patent References Cited: | 2006/0136797 June 2006 Cai 2019/0104121 April 2019 Khandani |
| Other References: | Chen et al. Improved Decoding of Staircase Codes: The Soft-Aided bit-marking (SABM) algorithm. eprint arXiv:1902.01178 Feb. 2019. cited by applicant |
| Primary Examiner: | Alphonse, Fritz |
| Attorney, Agent or Firm: | Lumen Patent Firm |
| Přístupové číslo: | edspgr.11251809 |
| Databáze: | USPTO Patent Grants |
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