Polar coding with dynamic frozen bits
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| Název: | Polar coding with dynamic frozen bits |
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| Patent Number: | 11108,411 |
| Datum vydání: | August 31, 2021 |
| Appl. No: | 16/657681 |
| Application Filed: | October 18, 2019 |
| Abstrakt: | The present application concerns an encoding device comprising a FC 11 configured to generate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits, wherein m≥2. In an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit. The present application also concerns a decoding device comprising a processor configured to decode successively a polar-coded-bitstream comprising m-polar decoding steps, wherein m≥2. In an i-th polar decoding step of the m polar decoding steps at least one frozen bit is based on at least one unfrozen bit. Further, the present application concerns also correspondingly arranged encoding and decoding methods. |
| Inventors: | HUAWEI TECHNOLOGIES DUESSELDORF GMBH (Duesseldorf, DE); TECHNISCHE UNIVERSITÄET MÜENCHEN (Munich, DE) |
| Assignees: | Huawei Technologies Duesseldorf GmbH (Duesseldorf, DE), Technische Universität München (Munich, DE) |
| Claim: | 1. An encoding device, comprising: an encoder configured to generate m number of FC-output-bit-sequences by executing m number of polar encoding steps upon m number of FC-input-bit-sequences, respectively, wherein each FC-input-bit-sequence of the m number of FC-input-bit-sequences comprises frozen bits and unfrozen bits, wherein m is an integer value and m≥2, wherein one of the m number of polar encoding steps is denoted as an i-th polar encoding step, and another one of the m number of polar encoding steps other than the i-th polar encoding step is denoted as a j-th polar encoding step, and wherein the j-th polar encoding step is performed prior to the i-th polar encoding step, wherein the i-th polar encoding step corresponds to an i-th FC-input-bit-sequence, wherein the j-th polar encoding step corresponds to a j-th FC-input-bit-sequence, and wherein at least one frozen bit of the i-th FC-input-bit-sequence is based on at least one unfrozen bit of the j-th FC-input-bit-sequence. |
| Claim: | 2. The encoding device of claim 1 , wherein j=1 and/or j=i−1. |
| Claim: | 3. The encoding device of claim 1 , further comprising: a postcoder configured to map the m FC-output-bit-sequences by a linear transformation to m system-output-bit sequences. |
| Claim: | 4. The encoding device of claim 3 , further comprising: a precoder configured to map a system-input-bit-sequence to the m FC-input-bit-sequences. |
| Claim: | 5. The encoding device of claim 4 , wherein the precoder comprises an inverse of the mapping of the m FC-input-bit-sequences to the m FC-output-bit-sequences or them system-output-bit-sequences. |
| Claim: | 6. The encoding device of claim 5 , wherein the precoder is configured to map bits of the m system-input-bit-sequences such that they appear at pre-defined positions in the m system-output-bit-sequences. |
| Claim: | 7. The encoding device of claim 5 , wherein the precoder is configured to map the m system-input-bit-sequences such that at least a subsequence of the m system-input-bit-sequences is comprised by the m system-output-bit-sequences. |
| Claim: | 8. The encoding device of claim 7 , wherein the precoder is configured to map bits of the system-input-bit-sequence such that parity bits appear at pre-defined positions. |
| Claim: | 9. The encoding device of claim 8 , further comprising: a shaping encoder configured to map an input-bit-sequence to the system-input-bit-sequence such that the system-input-bit-sequence is distributed non-uniformly. |
| Claim: | 10. The encoding device of claim 8 , wherein the pre-defined positions are in the m-th system-output-bit-sequence. |
| Claim: | 11. An encoding method, comprising: generating, by an encoder, m number of FC-output-bit-sequences by executing m number of polar encoding steps upon m number of FC-input-bit-sequences, respectively, wherein each FC-input-bit-sequence of the m number of FC-input-bit-sequences comprises frozen bits and unfrozen bits, wherein m is an integer value and m≥2, wherein one of the m number of polar encoding steps is denoted as an i-th polar encoding step, and another one of the m number of polar encoding steps other than the i-th polar encoding step is denoted as a j-th polar encoding step, and wherein the j-th polar encoding step is performed prior to the i-th polar encoding step, wherein the i-th polar encoding step corresponds to an i-th FC-input-bit-sequence, wherein the j-th polar encoding step corresponds to a j-th FC-input-bit-sequence, and wherein at least one frozen bit of the i-th FC-input-bit-sequence is based on at least one unfrozen bit of the j-th FC-input-bit-sequence. |
| Claim: | 12. A decoding device, comprising: a processor configured to decode successively a polar-coded-bitstream comprising m number of polar decoding steps, wherein m is an integer value and m≥2, wherein one of the m number of polar encoding steps is denoted as an i-th polar encoding step, and another one of the m number of polar encoding steps other than the i-th polar encoding step is denoted as a j-th polar encoding step, and wherein the j-th polar encoding step is performed prior to the i-th polar encoding step, wherein at least one frozen bit in the i-th polar decoding step is based on at least one unfrozen bit in the j-th polar decoding step. |
| Claim: | 13. The decoding device according to claim 12 , wherein j=1 and/or j=i−1. |
| Patent References Cited: | 8347186 January 2013 Arikan 8913686 December 2014 Barron 9164835 October 2015 Lee 9176927 November 2015 Gross 9362950 June 2016 Wiley 9467164 October 2016 Ionita 9628114 April 2017 Huang 9819361 November 2017 Shin 9954645 April 2018 Ahn 10461779 October 2019 Hong 2014/0019820 January 2014 Vardy 2015/0077277 March 2015 Alhussien 2015/0295593 October 2015 Trifonov et al. 2017/0149531 May 2017 Raza |
| Other References: | “Channel coding for control channels,” 3GPP TSG RAN WG1 Meeting #86, Gothenburg, Sweden, R1-167216, XP051142539, pp. 1-8, 3rd Generation Partnership Project, Valbonne, France (Aug. 22-26, 2016). cited by applicant “Details of the Polar code design,” 3GPP TSG RAN WG1 Meeting #87, Reno, USA, R1-1611254, XP051175235, pp. 1-16, 3rd Generation Partnership Project, Valbonne, France (Nov. 10-14, 2016). cited by applicant Tavildar “Bit-permuted Coded Modulation for Polar Codes,” XP055390429, pp. 1-6 (Sep. 30, 2016). cited by applicant Vangala et al., “A New Multiple Folded Successive Cancellation Decoder for Polar Codes,” XP032694569, pp. 381-385 (2014). cited by applicant Böcherer et al., “High Throughput Probabilistic Shaping with Product Distribution Matching,” XP080748436, pp. 1-10, Institute of Electrical and Electronics Engineers, New York, New York (Feb. 24, 2017). cited by applicant Böcherer et al., “Efficient Polar Code Construction for Higher-Order Modulation,” XP033093159, pp. 1-6, Institute of Electrical and Electronics Engineers, New York, New York (2017). cited by applicant |
| Primary Examiner: | Abraham, Esaw T |
| Attorney, Agent or Firm: | Leydig, Voit & Mayer, Ltd. |
| Přístupové číslo: | edspgr.11108411 |
| Databáze: | USPTO Patent Grants |
| Abstrakt: | The present application concerns an encoding device comprising a FC 11 configured to generate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits, wherein m≥2. In an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit. The present application also concerns a decoding device comprising a processor configured to decode successively a polar-coded-bitstream comprising m-polar decoding steps, wherein m≥2. In an i-th polar decoding step of the m polar decoding steps at least one frozen bit is based on at least one unfrozen bit. Further, the present application concerns also correspondingly arranged encoding and decoding methods. |
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