Dynamically adjustable cyclic redundancy code types
Uloženo v:
| Název: | Dynamically adjustable cyclic redundancy code types |
|---|---|
| Patent Number: | 10530,396 |
| Datum vydání: | January 07, 2020 |
| Appl. No: | 15/817387 |
| Application Filed: | November 20, 2017 |
| Abstrakt: | Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver. |
| Inventors: | International Business Machines Corporation (Armonk, NY, US) |
| Assignees: | INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY, US) |
| Claim: | 1. A computer-implemented method comprising: monitoring bits received at a receiver via a communication channel for transmission errors, the monitoring comprising: receiving frames of bits from a transmitter communicatively coupled to the receiver via the communication channel, at least one of the received frames comprising cyclic redundancy code (CRC) bits for a first type of CRC check; and determining whether a change in transmission errors has occurred in the received frames, the determining comprising performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames; and initiating, at the receiver, a change from the first type of CRC check to a second type of CRC check based at least in part on determining that a change in transmission error has occurred in the received frames, wherein the change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver. |
| Claim: | 2. The computer-implemented method of claim 1 , wherein the first type of CRC check performs frame isolation of errors and the second type of CRC check performs lane isolation of errors. |
| Claim: | 3. The computer-implemented method of claim 1 , further comprising, subsequent to initiating the change from the first type of CRC check to the second type of CRC check, initiating, at the receiver, a change from the second type of CRC check to the first type of CRC check based at least in part on determining that a second change in transmission errors has occurred, wherein the change from the second type of CRC check to the first type of CRC check is synchronized between the receiver and the transmitter. |
| Claim: | 4. The computer-implemented method of claim 1 , wherein the receiver is a distributed memory buffer, the transmitter is a host computer, the communication channel comprises a plurality of memory channels, and at least one of the plurality of memory channels is protected by the first type of CRC check and at least one of the other plurality of memory channels is protected by the second type of CRC check. |
| Claim: | 5. The computer-implemented method of claim 1 , wherein the receiver is a unified memory buffer, the transmitter is a host computer, and the communication channel is a memory channel. |
| Claim: | 6. The computer-implemented method of claim 1 , wherein frames of bits transmitted in different directions over the communication channel are protected by different types of CRC checks. |
| Claim: | 7. The computer-implemented method of claim 1 , wherein the change from the first type of CRC check to the second type of CRC check is performed in parallel with functional operations performed by the transmitter. |
| Claim: | 8. The computer-implemented method of claim 1 , further comprising: receiving a request from the transmitter to protect the memory channel using a third type of CRC check; and changing to the third type of CRC check at the receiver based on the request from the transmitter. |
| Claim: | 9. The computer implemented method of claim 1 , wherein the determining whether a change in transmissions errors has occurred in the received frames includes determining whether more than a threshold number of transmission errors have occurred in the received frames. |
| Claim: | 10. A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: monitoring bits received at a receiver via a communication channel for transmission errors, the monitoring comprising: receiving frames of bits from a transmitter communicatively coupled to the receiver via the communication channel, at least one of the received frames comprising cyclic redundancy code (CRC) bits for a first type of CRC check; and determining whether a change in transmission errors has occurred in the received frames, the determining comprising performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames; and initiating, at the receiver, a change from the first type of CRC check to a second type of CRC check based at least in part on determining that a change is transmission errors has occurred in the received frames, wherein the change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver. |
| Claim: | 11. The system of claim 10 , wherein the first type of CRC check performs frame isolation of errors and the second type of CRC check performs lane isolation of errors. |
| Claim: | 12. The system of claim 10 , wherein the operations further comprise, subsequent to initiating the change from the first type of CRC check to the second type of CRC check, initiating, at the receiver, a change to the first type of CRC check based at least in part on determining that a second change in transmission errors has occurred, wherein the change from the second type of CRC check to the first type of CRC check is synchronized between the receiver and the transmitter. |
| Claim: | 13. The system of claim 10 , wherein the receiver is a distributed memory buffer, the transmitter is a host computer, the communication channel comprises a plurality of memory channels, and at least one of the plurality of memory channels is protected by the first type of CRC check and at least one of the other plurality of memory channels is protected by the second type of CRC check. |
| Claim: | 14. The system of claim 10 , wherein the receiver is a unified memory buffer, the transmitter is a host computer, and the communication channel is a memory channel. |
| Claim: | 15. The system of claim 10 , wherein frames of bits transmitted in different directions over the communication channel are protected by different types of CRC checks. |
| Claim: | 16. The system of claim 10 , wherein the change to the second type of CRC check is performed in parallel with functional operations performed by the transmitter. |
| Claim: | 17. The system of claim 10 , wherein the operations further comprise: receiving a request from the transmitter to protect the memory channel using a third type of CRC check; and changing to the third type of CRC check at the receiver based on the request from the transmitter. |
| Claim: | 18. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising: monitoring bits received at a receiver via a communication channel for transmission errors, the monitoring comprising: receiving frames of bits from a transmitter communicatively coupled to the receiver via the communication channel, at least one of the received frames comprising cyclic redundancy code (CRC) bits for a first type of CRC check; and determining whether a change in transmission errors has occurred in the received frames, the determining comprising performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames; and initiating, at the receiver, a change from the first type of CRC check to a second type of CRC check based at least in part on determining that a change in transmission errors has occurred in the received frames, wherein the change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver. |
| Claim: | 19. The computer program product of claim 18 , wherein the receiver is a distributed memory buffer, the transmitter is a host computer, the communication channel comprises a plurality of memory channels, and at least one of the plurality of memory channels is protected by the first type of CRC check and at least one of the other plurality of memory channels is protected by the second type of CRC check. |
| Claim: | 20. The computer program product of claim 18 , wherein the receiver is a unified memory buffer, the transmitter is a host computer, and the communication channel is a memory channel. |
| Patent References Cited: | 5734826 March 1998 Olnowich et al. 5844918 December 1998 Kato 6175941 January 2001 Poeppelman 6522665 February 2003 Suzuki 6598189 July 2003 Zhao et al. 6601216 July 2003 Obata 6658076 December 2003 Hayata 6820228 November 2004 Keller 7047453 May 2006 Lappin, Jr. 7162683 January 2007 Bune 7227797 June 2007 Thayer 7411522 August 2008 Yamanshi 7523305 April 2009 Skovira 7613991 November 2009 Bain 8074150 December 2011 Buckley 8099651 January 2012 Normoyle et al. 8332721 December 2012 Lawson 8352830 January 2013 Landschaft 8601345 December 2013 Huang 9287896 March 2016 Seo 9298668 March 2016 Thayer 2002/0012343 January 2002 Holloway et al. 2003/0093743 May 2003 Berry, Jr. et al. 2004/0068689 April 2004 Saxena 2004/0123221 June 2004 Huffman et al. 2004/0158794 August 2004 Niesen 2005/0144222 June 2005 Anderson et al. 2005/0163235 July 2005 Mo et al. 2007/0297451 December 2007 Kim 2008/0186988 August 2008 Carmon 2010/0205518 August 2010 Golitschek Edler Von Elbwart et al. 2010/0287441 November 2010 Seo 2011/0004817 January 2011 Cheong et al. 2013/0080862 March 2013 Bennett 2013/0100012 April 2013 Todorovich et al. 2013/0132796 May 2013 Vummintala 2013/0145229 June 2013 Frayer 2013/0290802 October 2013 Busaba et al. 2013/0290803 October 2013 Busaba et al. 2014/0089516 March 2014 Sevin 2014/0328256 November 2014 Djukic 2015/0071620 March 2015 Keohane 2015/0378823 December 2015 Lesartre 2016/0087825 March 2016 Tian et al. 2016/0217030 July 2016 Shin 2017/0075754 March 2017 Wang 2018/0062787 March 2018 Hsieh 2019/0158126 May 2019 Carlough 2019/0158218 May 2019 Carlough 2019/0158223 May 2019 Carlough 1302382 April 2003 1826909 August 2007 1742498 October 2007 2264905 December 2010 2004086633 October 2004 2009156798 December 2009 2014204373 December 2014 2016108556 July 2016 |
| Other References: | Baicheva, “Determination of the Best CRC Codes with up to 10-Bit Redundancy”, IEEE, 2008, 7 pages. cited by applicant List of IBM Patents or Patent Applictions Treated As Related; (Appendix P), Filed Nov. 20, 2017, 2 pages. cited by applicant Steven R. Carloughl, et al., Pending U.S. Appl. No. 15/817,408 entitled “Dynamically Adjustable Cyclic Redundancy Code Rates,” filed with the U.S. Patent and Trademark Office on Nov. 20, 2017. cited by applicant Steven R. Carloughl, et al., Pending U.S. Appl. No. 15/817,416 entitled “Use of a Cyclic Redundancy Code Multiple-Input Shift Register to Provide Early Warning and Fail Detection ,” filed with the U.S. Patent and Trademark Office on Nov. 20, 2017. cited by applicant Steven R. Carloughl, et al., Pending U.S. Appl. No. 15/817,399 entitled “Use of Multiple Cyclic Redundancy Codes for Optimized Fail Isolation ,” filed with the U.S. Patent and Trademark Office on Nov. 20, 2017. cited by applicant Gangopadhyay et al., “Multiple-bit Parity-based Concurrent Fault Detection Architecture for Parallel CRC Computation”, IEEE, 2015, 14 pages. cited by applicant List of IBM Patents or Patent Applictions Treated As Related; (Appendix P), 2 pages. cited by applicant May, Phil, et al., “Improvement in bit-error rate for optoelectronic multicomputer interconnection networks using cyclic redundancy code error detection”, IEEE Photonics Technology Letters 9.6 (1997): 848-850. cited by applicant Moon, Jaekyun, et al.,“Cyclic redundancy check code based high-rate error-detection code for perpendicular recording”, IEEE transactions on magnetics 42.5 (2006): 1626-1628. cited by applicant Salmistraro et al., “Rate-adaptive BCH codes for distributed source coding”, Springer, 2013, 14 pages. cited by applicant |
| Primary Examiner: | Chaudry, Mujtaba M |
| Attorney, Agent or Firm: | Cantor Colburn LLP Bortnick, Bryan |
| Přístupové číslo: | edspgr.10530396 |
| Databáze: | USPTO Patent Grants |
Buďte první, kdo okomentuje tento záznam!