Efficient check node message transform approximation for LDPC decoder
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| Název: | Efficient check node message transform approximation for LDPC decoder |
|---|---|
| Patent Number: | 8,495,119 |
| Datum vydání: | July 23, 2013 |
| Appl. No: | 12/348674 |
| Application Filed: | January 05, 2009 |
| Abstrakt: | In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp functions is described which involves using a simple bit mapping between fixed point fractional data format and floating point format. The method avoids costly lookup tables and complex computations and further reduces the core processing to a sequence of additions and subtractions using alternating fixed point and floating point processing units. The method is well suited for use in highly optimized hardware implementations which can take advantage of modern advances in standard floating point arithmetic circuit design as well as for software implementation on a wide class of processors equipped with FPU where the invention avoids the need for a typical multi-cycle series of log/exp instructions and especially on a SIMD FPU-equipped processors where log/exp functions are typically scalar. |
| Inventors: | Novichkov, Vladimir (Towaco, NJ, US); Richardson, Tom (South Orange, NJ, US) |
| Assignees: | QUALCOMM Incorporated (San Diego, CA, US) |
| Claim: | 1. A decoder comprising: a memory configured to store an input value having an integer part and a fractional part; and mapping circuitry coupled to the memory and configured to calculate a floating point number having an exponent value mapped from the integer part by inserting the inter part into an exponent field of the floating point number to generate the exponent value and further having a significand value mapped from the fractional part by inserting the fractional part into a significand field of the floating point number to generate the significand value. |
| Claim: | 2. The decoder of claim 1 wherein the decoder is one of a low density parity check decoder, and a turbo-convolutional decoder. |
| Claim: | 3. The decoder of claim 1 wherein the mapping circuitry is further configured to approximate an exponentiation operation that corresponds to calculating 2 k-x , wherein x corresponds to the input value and k corresponds to a scaling value. |
| Claim: | 4. The decoder of claim 3 wherein the exponentiation operation is a base ten exponentiation operation. |
| Claim: | 5. The decoder of claim 3 wherein the exponentiation operation is a base two exponentiation operation. |
| Claim: | 6. The decoder of claim 1 further comprising: floating point processing circuitry configured to generate a floating point output value based at least in part on the floating point number; and second mapping circuitry configured to calculate a fixed point fractional output value by inserting an exponent part of the floating point output value into an integer field of the fixed point fractional output value and by inserting a significand part of the floating point output value into a fractional field of the fixed point fractional output value. |
| Claim: | 7. A decoder comprising: means for storing an input value having an integer part and a fractional part; and means for mapping the integer part to an exponent value by inserting the integer part into an exponent field of a floating point number to generate the exponent value and for mapping the fractional part to a significand value by inserting the fractional part into a significand field of the floating point number to generate the significand value. |
| Claim: | 8. The decoder of claim 7 wherein the decoder is a low density parity check decoder and the mapping means is configured to perform a bit-wise inversion operation. |
| Claim: | 9. The decoder of claim 7 wherein the decoder is a turbo-convolutional decoder. |
| Claim: | 10. The decoder of claim 7 further comprising: means for generating a floating point output value based at least in part on the floating point number; and means for calculating a fixed point fractional output value by inserting an exponent part of the floating point output value into an integer field of the fixed point fractional output value and by inserting a significand part of the floating point output value into a fractional field of the fixed point fractional output value. |
| Claim: | 11. A computer-readable tangible medium storing instructions executable by a computer, the instructions comprising: instructions that are executable by the computer to store an input value in memory, the input value having an integer part and a fractional part; and instructions that are executable by the computer to map the integer part to an exponent value by inserting the integer part into an exponent field of a floating point number to generate the exponent value and that are further executable by the computer to map the fractional part to a significand value by inserting the fractional part into a significand field of the floating point number to generate the significand value. |
| Claim: | 12. The computer-readable tangible medium of claim 11 wherein mapping the integer part and the fractional part is performed in a low density parity check decoder. |
| Claim: | 13. The computer-readable tangible medium of claim 11 wherein mapping the integer part and the fractional part is performed in a turbo-convolutional decoder. |
| Claim: | 14. A method comprising: generating, by first mapping circuitry, a first floating point value having a floating point format at least in part by performing a first interpretation change operation with respect to a first fixed fractional point value having a fixed fractional point format; performing, by floating point processing circuitry, at least one operation based on the first floating point value to generate a second floating point value; and generating, by second mapping circuitry, a second fixed fractional point value having the fixed fractional point format at least in part by performing a second interpretation change operation with respect to the second floating point value. |
| Claim: | 15. The method of claim 14 , wherein performing the first interpretation change operation includes directly mapping an integer portion of the first fixed fractional point value to an exponent portion of the first floating point value and further includes directly mapping a fractional portion of the first fixed fractional point value to a significand portion of the first floating point value. |
| Claim: | 16. The method of claim 14 , wherein generating the first floating point value approximates negating, scaling, and exponentiating the first fixed fractional point value. |
| Claim: | 17. The method of claim 16 , wherein generating the first floating point value approximates 2 k-x , wherein x corresponds to the first fixed fractional point value and k corresponds to a scaling value. |
| Claim: | 18. The method of claim 14 , wherein performing the second interpretation change operation directly converts the second floating point value from the floating point format to the fixed fractional point format, and wherein performing the first interpretation change operation does not include calling a logarithm function and further does not include performing a type conversion operation. |
| Current U.S. Class: | 708/277 |
| Patent References Cited: | 4583180 April 1986 Kmetz 5365465 November 1994 Larson 5798957 August 1998 Pan et al. 6144977 November 2000 Giangarra et al. 6633856 October 2003 Richardson et al. 6671796 December 2003 Sudharsanan et al. 6785863 August 2004 Blankenship et al. 6938196 August 2005 Richardson et al. 7475103 January 2009 Novichkov et al. 7644116 January 2010 Tandon et al. 2003/0005006 January 2003 Chatterjee 2003/0014453 January 2003 Challa et al. 2003/0101206 May 2003 Graziano et al. 2007/0282936 December 2007 Tandon et al. 405093 September 2000 412690 November 2000 440814 June 2001 466843 December 2001 200500878 January 2005 |
| Other References: | “Logarithmic fixed-point number” [Online] Sep. 24, 2004, p. 1, XP002407457 Retrieved from the Internet: URL:http//books.w3k.org/html/mdft.Logarit hmic—Fixed—Point—Numbers.html>[retrieved on Nov. 15, 2006] the whole document. cited by applicant J.F. Blinn: “Floating-Point Tricks” IEEE Computer Graphics and Applications, (Online) vol. 17, No. 4, Aug. 1997, pp. 80-84, XP002407431, Retrieved from the Internet URL:http//ieeeexplore.ieee.org/iell/38/13035/0595279.pdf? Arnumber=595279> [retrieve. cited by applicant NN: “Adding floating point numbers” [Online] Oct. 21, 2004, pp. 1-3, XP002407432 Retrieved from Internet: URL:http//web,archive.org/web/2004107014905/http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/BinMath/addFloat.html>[retrieved on Nov. 15, 2006]. cited by applicant NN: Creating a one byte floating point number [Online] Oct. 21, 2004, pp. 1-2. XP002407433 Retrieved from the Internet: URL:http//web.archive.org/web/20041027021345/www.cs.umd.edu/class/spring2003/cms31 1/Notes/BinMath/byteFloat.html>[retrieved on 20. cited by applicant International Search Report—PCT/US2006/009839—International Search Authority—European Patent Office—Dec. 5, 2006. cited by applicant International Preliminary Report—PCT/US2006/009839, International Search Authority—European Patent Office—Apr. 3, 2007. cited by applicant Written Opinion—PCT/US2006/009839, International Search Authority—European Patent Office—Dec. 5, 2006. cited by applicant Taiwan Search Report—TW095109239—TIPO—May 17, 2012. cited by applicant |
| Primary Examiner: | Malzahn, David H |
| Attorney, Agent or Firm: | Talpalatsky, Sam Pauley, Nicholas J. Agusta, Joseph |
| Přístupové číslo: | edspgr.08495119 |
| Databáze: | USPTO Patent Grants |
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