PAM-BASED CODING SCHEMES FOR PARALLEL COMMUNICATION
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| Název: | PAM-BASED CODING SCHEMES FOR PARALLEL COMMUNICATION |
|---|---|
| Document Number: | 20210234618 |
| Datum vydání: | July 29, 2021 |
| Appl. No: | 16/752542 |
| Application Filed: | January 24, 2020 |
| Abstrakt: | Encoders and decoders for encoding and decoding data according to a coding scheme. The encoder converts N bits of input data into M voltage signals for transmission over M parallel wires to a decoder having one or two decoding stages that recover the N bits of data from the M voltage signals. The coding scheme is an N-bit, M-wire PAM-Q code in which each voltage signal wi has one of Q voltage levels I1-IQ, where I1 |
| Assignees: | Nokia Solutions and Networks Oy (Espoo, FI), Technische Universität München (Munich, DE) |
| Claim: | 1. An article of manufacture comprising an encoder for encoding data according to a coding scheme, the encoder comprising: a first coding stage configured to convert N bits b1-bN of input data into P bits of intermediate data; and a second coding stage configured to convert the P bits of intermediate data into M voltage signals w1-wM for transmission over M parallel wires to a decoder, wherein: the coding scheme is an N-bit, M-wire PAM-Q code in which (i) each N-bit input value is encoded as a set of M voltage signals w1-wM, (ii) each voltage signal wi has one of Q voltage levels I1-IQ, where I1 |
| Claim: | 2. The article of claim 1, wherein N=M=Q=4. |
| Claim: | 3. The article of claim 2, wherein the 4-bit, 4-wire PAM4 code is represented as: [table included] |
| Claim: | 4. The article of claim 1, wherein N=4, M=5, and Q=3. |
| Claim: | 5. The article of claim 4, wherein the 4-bit, 5-wire PAM3 code is represented as: [table included] |
| Claim: | 6. The article of claim 1, wherein N=4, M=5, and Q=4. |
| Claim: | 7. The article of claim 6, wherein the 4-bit, 5-wire PAM4 code is represented as: [table included] |
| Claim: | 8. An article of manufacture comprising a decoder for decoding signals generated using a coding scheme, the decoder comprising one or two decoding stages including a first decoding stage, wherein: the first decoding stage is configured to receive M voltage signals w1-wM from M parallel wires; the decoder is configured to recover N bits b1-bN of data from the M voltage signals w1-wM; the coding scheme is an N-bit, M-wire PAM-Q code in which (i) each N-bit input value is encoded as a set of M voltage signals w1-wM, (ii) each voltage signal wi has one of Q voltage levels where I1 |
| Claim: | 9. The article of claim 8, wherein N=M=Q=4. |
| Claim: | 10. The article of claim 9, wherein the 4-bit, 4-wire PAM4 code is represented as: [table included] |
| Claim: | 11. The article of claim 10, wherein the decoder comprises a comparator stage followed by a computation stage. |
| Claim: | 12. The article of claim 11, wherein the decoder decodes the 4 voltage signals w1-w4 according to: b4=1(w4>w3); b3=1(w3>w2); b2=1(w3>w1); and b1=1(w2>w1)+1(w4>w2)−1(w4>w1). |
| Claim: | 13. The article of claim 10, wherein the decoder comprises a comparator stage followed by a logic stage. |
| Claim: | 14. The article of claim 13, wherein the decoder decodes the 4 voltage signals according to: b4=1(w4>w3); b3=1(w3>w2); b2=1(w3>w1); and b1=1(w2>w1)XOR 1(w4>w2)XOR 1(w4>w1). |
| Claim: | 15. The article of claim 8, wherein N=4, M=5, and Q=3. |
| Claim: | 16. The article of claim 15, wherein the 4-bit, 5-wire PAM3 code is represented as: [table included] |
| Claim: | 17. The article of claim 16, wherein the decoder comprises a computation stage followed by a comparator stage. |
| Claim: | 18. The article of claim 17, wherein the decoder decodes the 5 voltage signals according to: b4=1(w5>w4); b3=1((w3+w2)/2>w1); b2=1(w3>w2); and b1=1((w1+w2+w3)/3>(w4+w5)/2. |
| Claim: | 19. The article of claim 8, wherein N=4, M=5, and Q=4. |
| Claim: | 20. The article of claim 19, wherein the 4-bit, 5-wire PAM4 code is represented as: [table included] |
| Claim: | 21. The article of claim 20, wherein the decoder comprises a computation stage followed by a comparator stage. |
| Claim: | 22. The article of claim 21, wherein the decoder decodes the 5 voltage signals according to: b4=1(w5>w4); b3=1((w3+w2)/2>w1); b2=1(w3>w2); and b1=1((w1+w2+w3)/3>(w4+w5)/2. |
| Current International Class: | 04 |
| Přístupové číslo: | edspap.20210234618 |
| Databáze: | USPTO Patent Applications |
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