Reification: A Process to Configure Java Realtime Processors
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| Titel: | Reification: A Process to Configure Java Realtime Processors |
|---|---|
| Autoren: | Heath, John Huddleston |
| Quelle: | Dissertations |
| Verlagsinformationen: | The Aquila Digital Community |
| Publikationsjahr: | 2012 |
| Bestand: | The University of Southern Mississippi: The Aquila Digital Community |
| Schlagwörter: | real-time systems, WCET, cache and instruction pipelining, Computer Sciences, Physics |
| Beschreibung: | Real-time systems require stringent requirements both on the processor and the software application. The primary concern is speed and the predictability of execution times. In all real-time applications the developer must identify and calculate the worst case execution times (WCET) of their software. In almost all cases the processor design complexity impacts the analysis when calculating the WCET. Design features which impact this analysis include cache and instruction pipelining. With both cache and pipelining the time taken for a particular instruction can vary depending on cache and pipeline contents. When calculating the WCET the developer must ignore the speed advantages from these enhancements and use the normal instruction timings. This investigation is about a Java processor targeted to run within an FPGA environment (Java soft chip) supporting Java real-time applications. The investigation focuses on a simple processor design that allows simple analysis of WCET. The processor design has no cache and no instruction pipeline enhancements yet achieves higher performance than existing designs with these enhancements. The investigation centers on a process that translates Java byte codes and folds these translated codes into a modified Harvard Micro Controller (HMC). The modifications include better alignment with the application code and take advantage of the FPGA’s parallel capability. A prototyped ontology is used where the top level categories defined by Sowa are expanded to support the process. The proposed HMC and process are used to produce investigation results. Performance testing using the Sobel edge detection algorithm is used to compare the results with the only Java processor claiming real-time abilities. |
| Publikationsart: | text |
| Dateibeschreibung: | application/pdf |
| Sprache: | unknown |
| Relation: | https://aquila.usm.edu/dissertations/718; https://aquila.usm.edu/context/dissertations/article/1740/viewcontent/John_Huddleston_Heath__December_2012.pdf |
| Verfügbarkeit: | https://aquila.usm.edu/dissertations/718 https://aquila.usm.edu/context/dissertations/article/1740/viewcontent/John_Huddleston_Heath__December_2012.pdf |
| Dokumentencode: | edsbas.DAABEE56 |
| Datenbank: | BASE |
Nájsť tento článok vo Web of Science | Abstract: | Real-time systems require stringent requirements both on the processor and the software application. The primary concern is speed and the predictability of execution times. In all real-time applications the developer must identify and calculate the worst case execution times (WCET) of their software. In almost all cases the processor design complexity impacts the analysis when calculating the WCET. Design features which impact this analysis include cache and instruction pipelining. With both cache and pipelining the time taken for a particular instruction can vary depending on cache and pipeline contents. When calculating the WCET the developer must ignore the speed advantages from these enhancements and use the normal instruction timings. This investigation is about a Java processor targeted to run within an FPGA environment (Java soft chip) supporting Java real-time applications. The investigation focuses on a simple processor design that allows simple analysis of WCET. The processor design has no cache and no instruction pipeline enhancements yet achieves higher performance than existing designs with these enhancements. The investigation centers on a process that translates Java byte codes and folds these translated codes into a modified Harvard Micro Controller (HMC). The modifications include better alignment with the application code and take advantage of the FPGA’s parallel capability. A prototyped ontology is used where the top level categories defined by Sowa are expanded to support the process. The proposed HMC and process are used to produce investigation results. Performance testing using the Sobel edge detection algorithm is used to compare the results with the only Java processor claiming real-time abilities. |
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