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A garbage collection design and bakeoff in JMTk: An efficient extensible Java memory management toolkit

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Název: A garbage collection design and bakeoff in JMTk: An efficient extensible Java memory management toolkit
Autoři: Peter Strazdins, Bill Clarke Solemn, Stephen M Blackburn, Perry Cheng, Kathryn S Mckinley, Thomas A O'callaghan, James Popple, Eric Mccreath
Přispěvatelé: The Pennsylvania State University CiteSeerX Archives
Zdroj: https://openresearch-repository.anu.edu.au/bitstream/1885/43096/2/TR-CS-05-01.pdf.
Sbírka: CiteSeerX
Popis: This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the UltraSPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully implementing the CPU pipeline and microarchitecture. The main functions of the module are the simulation of instruction grouping, register interlocks and the store buffer, and has a simple tabledriven implementation which permits easy modification for exploring microarchitectural variations. The technique results on a 15-30% loss of simulation speed, instead of a 10 × or greater performance loss by fully implementing the detailed micro-architecture. The accuracy of the technique is validated against an actual UltraSPARC III Cu processor, and achieves high levels of accuracy in cases of itnerest.
Druh dokumentu: text
Popis souboru: application/pdf
Jazyk: English
Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1081.4127
Dostupnost: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1081.4127
Rights: Metadata may be used without restrictions as long as the oai identifier remains attached to it.
Přístupové číslo: edsbas.962B154C
Databáze: BASE
Popis
Abstrakt:This paper presents a novel technique for cycle-accurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the UltraSPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully implementing the CPU pipeline and microarchitecture. The main functions of the module are the simulation of instruction grouping, register interlocks and the store buffer, and has a simple tabledriven implementation which permits easy modification for exploring microarchitectural variations. The technique results on a 15-30% loss of simulation speed, instead of a 10 × or greater performance loss by fully implementing the detailed micro-architecture. The accuracy of the technique is validated against an actual UltraSPARC III Cu processor, and achieves high levels of accuracy in cases of itnerest.