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Ultra-high-throughput EMS NB-LDPC decoder with full-parallel node processing

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Title: Ultra-high-throughput EMS NB-LDPC decoder with full-parallel node processing
Authors: Harb, Hassan, Chamas Al Ghouwayel, Ali, Conde-Canencia, Laura, Marchand, Cédric, Boutillon, Emmanuel
Contributors: Lab-STICC_UBS_CACS_IAS, Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC), École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université Bretagne Loire (UBL)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom Paris (IMT), Lebanese International University (LIU), Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)-Université européenne de Bretagne - European University of Brittany (UEB)-École Nationale d'Ingénieurs de Brest (ENIB)-Université de Bretagne Sud (UBS)-Université de Brest (UBO)-Télécom Bretagne-Institut Brestois du Numérique et des Mathématiques (IBNM), Université de Brest (UBO)-École Nationale Supérieure de Techniques Avancées Bretagne (ENSTA Bretagne)-Institut Mines-Télécom Paris (IMT)-Centre National de la Recherche Scientifique (CNRS)
Source: https://hal.science/hal-02494736 ; 2020.
Publisher Information: CCSD
Publication Year: 2020
Collection: Université de Bretagne Sud: HAL
Subject Terms: Index Terms-Channel coding, decoder implementation, ASIC, non-binary LDPC, Min-Sum, parity check, [SPI.TRON]Engineering Sciences [physics]/Electronics
Description: This paper presents an ultra-high-throughput de-coder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one line of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N,K) = (144, 120) symbols over GF(64). The synthesis results on 28-nm technology show that the proposed architecture improves the throughput efficiency of the state of the art by a factor greater than 10. The architecture reaches a throughput above 10 Gb/s for SNR values greater than 5 dB. Compared to a 5G binary LDPC code of same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10 − 3. The proposed architecture reduces the required memory bandwidth by almost 50 % compared to a classical LDPC code. We also provide a detailed comparison with competitive state-of-the-art NB-LDPC decoder implementations in terms of performance, surface and decoding throughput are given.
Document Type: report
Language: English
Availability: https://hal.science/hal-02494736
https://hal.science/hal-02494736v2/document
https://hal.science/hal-02494736v2/file/TCAS_I_high_throughput_architectures.pdf
Rights: info:eu-repo/semantics/OpenAccess
Accession Number: edsbas.56E91B2F
Database: BASE
Description
Abstract:This paper presents an ultra-high-throughput de-coder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one line of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N,K) = (144, 120) symbols over GF(64). The synthesis results on 28-nm technology show that the proposed architecture improves the throughput efficiency of the state of the art by a factor greater than 10. The architecture reaches a throughput above 10 Gb/s for SNR values greater than 5 dB. Compared to a 5G binary LDPC code of same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10 − 3. The proposed architecture reduces the required memory bandwidth by almost 50 % compared to a classical LDPC code. We also provide a detailed comparison with competitive state-of-the-art NB-LDPC decoder implementations in terms of performance, surface and decoding throughput are given.