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Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography

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Název: Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
Autoři: Xie, Jiafeng, He, Pengzhou, Wang, Xiaofang, Imaña Pascual, José Luis
Informace o vydavateli: IEEE Institute of Electrical and Electronics Engineers
Rok vydání: 2022
Sbírka: Universidad Complutense de Madrid (UCM): E-Prints Complutense
Témata: 004.8, Multipliers, Parallel, Binary ring-learning-with-errors, Finite field arithmetic, FPGA platform, Hardware design, Post-quantum cryptography, Inteligencia artificial (Informática), 1203.04 Inteligencia Artificial
Popis: (c) 2022 IEEE Institute of Electrical and Electronics Engineers The work of Jiafeng Xie was supported by the NSFAward under Grants 2020625 and NIST-60NANB20D203. The work of Jose L. Imaña was supported by the Spanish MINECO and CM under Grants S2018/TCS-4423 and RTI2018-093684-B-I00. ; Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of inter-dependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications. ; Ministerio de Ciencia e Innovación (MICINN) /FEDER ; Comunidad de Madrid ; Sección Deptal. de Arquitectura de Computadores y Automática (Físicas) ; Fac. de Ciencias Físicas ; TRUE ; pub
Druh dokumentu: article in journal/newspaper
Popis souboru: application/pdf
Jazyk: English
Relation: RTI2018-093684-B-I00; CABAHLA-CM (S2018/TCS-4423); https://hdl.handle.net/20.500.14352/71695
DOI: 10.1109/TETC.2021.3091982
Dostupnost: https://hdl.handle.net/20.500.14352/71695
https://doi.org/10.1109/TETC.2021.3091982
Rights: open access
Přístupové číslo: edsbas.2C4F08A2
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  Data: Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
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  Data: <searchLink fieldCode="AR" term="%22Xie%2C+Jiafeng%22">Xie, Jiafeng</searchLink><br /><searchLink fieldCode="AR" term="%22He%2C+Pengzhou%22">He, Pengzhou</searchLink><br /><searchLink fieldCode="AR" term="%22Wang%2C+Xiaofang%22">Wang, Xiaofang</searchLink><br /><searchLink fieldCode="AR" term="%22Imaña+Pascual%2C+José+Luis%22">Imaña Pascual, José Luis</searchLink>
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  Data: 2022
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  Data: (c) 2022 IEEE Institute of Electrical and Electronics Engineers The work of Jiafeng Xie was supported by the NSFAward under Grants 2020625 and NIST-60NANB20D203. The work of Jose L. Imaña was supported by the Spanish MINECO and CM under Grants S2018/TCS-4423 and RTI2018-093684-B-I00. ; Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of inter-dependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications. ; Ministerio de Ciencia e Innovación (MICINN) /FEDER ; Comunidad de Madrid ; Sección Deptal. de Arquitectura de Computadores y Automática (Físicas) ; Fac. de Ciencias Físicas ; TRUE ; pub
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  Data: 10.1109/TETC.2021.3091982
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