APA (7th ed.) Citation

Liu, Q., Constantinides, G. A., Masselos, K., Cheung, P. Y. K., & Archives, T. P. S. U. C. (2008). Combining data reuse exploitation with data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf.

Chicago Style (17th ed.) Citation

Liu, Qiang, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung, and The Pennsylvania State University CiteSeerX Archives. "Combining Data Reuse Exploitation with Data-level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework." Http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf 2008.

MLA (9th ed.) Citation

Liu, Qiang, et al. "Combining Data Reuse Exploitation with Data-level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework." Http://cas.ee.ic.ac.uk/people/gac1/pubs/QiangFPL08.pdf, 2008.