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An Efficient Computer Vision AI Powered Application based Fast Harris Corner Detection Accelerator on Zynq-7000 FPGA

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Názov: An Efficient Computer Vision AI Powered Application based Fast Harris Corner Detection Accelerator on Zynq-7000 FPGA
Autori: Mohammad H Algarni, Taoufik Saidani
Zdroj: International Journal of Intelligent Systems and Applications in Engineering; Vol. 12 No. 3 (2024); 2450-2457
Informácie o vydavateľovi: International Journal of Intelligent Systems and Applications in Engineering, 2024.
Rok vydania: 2024
Predmety: HDL, HDL Coder, Fast Harris corner detection, Computer vision, Artificial Intelligence, Object Detection
Popis: Tools for rapid prototyping have been crucial in the race to market. A frequently-used computer vision, object detection and Artificial Intelligence tool for image processing, real-time contrast enhancement, is the focus of our study as we investigate the possibility of developing an intellectual property core using a fast prototyping technique. In this research paper, we provide a new method that uses HDL Coder-based high-level synthesis (HLS) rapidly to prototype fast corner detection on FPGAs. Implementing image processing algorithms on FPGAs using traditional RTL-based design approaches may prove a tedious, error-prone procedure. By providing a more abstract level of description, HLS frees up designers to concentrate on algorithmic functionality rather than writing inefficient hardware specifications by hand. We employ this feature by using the Harris corner detection method in MATLAB/Simulink, then using the HDL Coder methodology automatically to transform it into generated VHDL code that can be synthesized on Zynq7000 FPGA. Compared to the conventional RTL method, this design flow drastically reduces the development time and complexity. The suggested method for rapid FPGA prototyping in image processing applications is demonstrated to be successful by our practical findings, which indicate that the HLS-based Harris corner detector achieves the performance of real time video processing on a Xilinx Zynq7000 FPGA platform.
Druh dokumentu: Article
Popis súboru: application/pdf
Jazyk: English
ISSN: 2147-6799
Prístupová URL adresa: https://www.ijisae.org/index.php/IJISAE/article/view/5716
Rights: CC BY SA
Prístupové číslo: edsair.issn21476799..bb5809e7a9ddadaee32c770a16f1ac16
Databáza: OpenAIRE
Popis
Abstrakt:Tools for rapid prototyping have been crucial in the race to market. A frequently-used computer vision, object detection and Artificial Intelligence tool for image processing, real-time contrast enhancement, is the focus of our study as we investigate the possibility of developing an intellectual property core using a fast prototyping technique. In this research paper, we provide a new method that uses HDL Coder-based high-level synthesis (HLS) rapidly to prototype fast corner detection on FPGAs. Implementing image processing algorithms on FPGAs using traditional RTL-based design approaches may prove a tedious, error-prone procedure. By providing a more abstract level of description, HLS frees up designers to concentrate on algorithmic functionality rather than writing inefficient hardware specifications by hand. We employ this feature by using the Harris corner detection method in MATLAB/Simulink, then using the HDL Coder methodology automatically to transform it into generated VHDL code that can be synthesized on Zynq7000 FPGA. Compared to the conventional RTL method, this design flow drastically reduces the development time and complexity. The suggested method for rapid FPGA prototyping in image processing applications is demonstrated to be successful by our practical findings, which indicate that the HLS-based Harris corner detector achieves the performance of real time video processing on a Xilinx Zynq7000 FPGA platform.
ISSN:21476799