Run-Time Reconfiguration for Automatic Hardware/Software Partitioning
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| Názov: | Run-Time Reconfiguration for Automatic Hardware/Software Partitioning |
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| Autori: | Davidson, Tom, Bruneel, Karel, Stroobandt, Dirk |
| Prispievatelia: | Prasanna, V, Becker, J, Cumplido, R |
| Zdroj: | Proceedings 2010 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2010) |
| Informácie o vydavateľovi: | IEEE, 2010. |
| Rok vydania: | 2010 |
| Predmety: | Technology and Engineering, AES, run-time reconfiguration, dynamic reconfiguration, hardware/software partitioning, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, FPGA |
| Popis: | Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware implementation for area by converting it automatically to a hardware/software implementation. This tool flow can partition the design in a very short time and, at the same time, result in significant area gains. The usage of run time reconfiguration allows us to extend the hardware/software boundary so more functionality can be moved to software. We will explain the core principles behind the run-time reconfiguration technique using the AES encoder as an example. For the AES encoder the manual hardware/software partitioning is clear. This manual partitioning will serve as a comparison to the automated partitioning that uses parameterisable configurations. Several possible AES encoder implementations are compared. Our automatically partitioned AES design shows a 20.6 % area gain compared to an unoptimized hardware implementation and a 5.3 % gain compared to a manually optimized 3rd party hardware implementation. In addition, we discuss the results of our technique on other applications, where the hardware/software partitioning is less clear. Among these, a TripleDES implementation shows a 29.3 % area gain using our technique. Based on our AES encoder results, we derive some guidelines for optimizing the impact of parameterisable configurations in general designs. |
| Druh dokumentu: | Article Conference object |
| Popis súboru: | application/pdf |
| DOI: | 10.1109/reconfig.2010.57 |
| Prístupová URL adresa: | https://biblio.ugent.be/publication/1105031/file/1148368.pdf https://dblp.uni-trier.de/db/conf/reconfig/reconfig2010.html#DavidsonBS10 https://biblio.ugent.be/publication/1105031 https://biblio.ugent.be/publication/1105031/file/1148368.pdf https://www.computer.org/csdl/proceedings/reconfig/2010/4314/00/4314a424.pdf http://ieeexplore.ieee.org/document/5695343/ http://doi.org/10.1109/ReConFig.2010.57 http://hdl.handle.net/1854/LU-1105031 https://biblio.ugent.be/publication/1105031/file/1148368 https://biblio.ugent.be/publication/1105031 |
| Prístupové číslo: | edsair.doi.dedup.....f1c09b4aa20b49e53d7f0f6f2b7f01c0 |
| Databáza: | OpenAIRE |
Nájsť tento článok vo Web of Science | Abstrakt: | Parameterisable configurations allow very fast run-time reconfiguration in FPGAs. The main advantage of this new concept is the automated tool flow that converts a hardware design into a more resource-efficient run-time reconfigurable design without a large design effort. In this paper, we show that the automated tool flow for run-time reconfiguration can be used to easily optimize a full hardware implementation for area by converting it automatically to a hardware/software implementation. This tool flow can partition the design in a very short time and, at the same time, result in significant area gains. The usage of run time reconfiguration allows us to extend the hardware/software boundary so more functionality can be moved to software. We will explain the core principles behind the run-time reconfiguration technique using the AES encoder as an example. For the AES encoder the manual hardware/software partitioning is clear. This manual partitioning will serve as a comparison to the automated partitioning that uses parameterisable configurations. Several possible AES encoder implementations are compared. Our automatically partitioned AES design shows a 20.6 % area gain compared to an unoptimized hardware implementation and a 5.3 % gain compared to a manually optimized 3rd party hardware implementation. In addition, we discuss the results of our technique on other applications, where the hardware/software partitioning is less clear. Among these, a TripleDES implementation shows a 29.3 % area gain using our technique. Based on our AES encoder results, we derive some guidelines for optimizing the impact of parameterisable configurations in general designs. |
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| DOI: | 10.1109/reconfig.2010.57 |