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Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative

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Bibliographic Details
Title: Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative
Authors: Nannipieri, Pietro, Crocetti, Luca, Di Matteo, Stefano, Fanucci, Luca, Saponara, Sergio
Source: IEEE Transactions on Computers. 74:762-775
Publisher Information: Institute of Electrical and Electronics Engineers (IEEE), 2025.
Publication Year: 2025
Subject Terms: AES, ECC, RNG, SHA, RISC-V, EPI, Cryptoprocessor, Hardware, Security, Root of Trust, Chain of Trust, Secure boot
Description: This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each of the coprocessors of Crypto-Tile is dedicated to a specific family of cryptographic algorithms, offering functions for symmetric and public-key cryptography, computation of digests, generation of random numbers, and Post-Quantum cryptography. The performances of each coprocessor outperform other available solutions, offering innovative hardware-native services, such as key management, clock randomisation and access privilege mechanisms. The system has been synthesised on a 7 nm standard-cell technology, being the first Cryptoprocessor to be characterised in such an advanced silicon technology. The post-synthesis netlist has been employed to assess the resistance of Crypto-Tile to power analysis side-channel attacks. Finally, a demoboard has been implemented, integrating a RISC-V softcore processor and the Crypto-Tile module, and drivers for hardware abstraction layer, bare-metal applications and drivers for Linux kernel in C language have been developed. Finally, we exploited them to compare in terms of execution speed the hardware-accelerated algorithms against software-only solutions.
Document Type: Article
File Description: application/pdf
ISSN: 2326-3814
0018-9340
DOI: 10.1109/tc.2023.3278536
Access URL: https://ieeexplore.ieee.org/document/10130378
https://hdl.handle.net/11568/1180007
https://doi.org/10.1109/TC.2023.3278536
Rights: CC BY NC ND
Accession Number: edsair.doi.dedup.....5febd646b51f01a5aa76bcae3b72dedd
Database: OpenAIRE
Description
Abstract:This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each of the coprocessors of Crypto-Tile is dedicated to a specific family of cryptographic algorithms, offering functions for symmetric and public-key cryptography, computation of digests, generation of random numbers, and Post-Quantum cryptography. The performances of each coprocessor outperform other available solutions, offering innovative hardware-native services, such as key management, clock randomisation and access privilege mechanisms. The system has been synthesised on a 7 nm standard-cell technology, being the first Cryptoprocessor to be characterised in such an advanced silicon technology. The post-synthesis netlist has been employed to assess the resistance of Crypto-Tile to power analysis side-channel attacks. Finally, a demoboard has been implemented, integrating a RISC-V softcore processor and the Crypto-Tile module, and drivers for hardware abstraction layer, bare-metal applications and drivers for Linux kernel in C language have been developed. Finally, we exploited them to compare in terms of execution speed the hardware-accelerated algorithms against software-only solutions.
ISSN:23263814
00189340
DOI:10.1109/tc.2023.3278536