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An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator

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Bibliographic Details
Title: An Integrated Solution to Improve Performance of In-Memory Data Caching With an Efficient Item Retrieving Mechanism and a Near-Memory Accelerator
Authors: Minkwan Kee, Chiwon Han, Gi-Ho Park
Source: IEEE Access, Vol 11, Pp 78726-78736 (2023)
Publisher Information: Institute of Electrical and Electronics Engineers (IEEE), 2023.
Publication Year: 2023
Subject Terms: linked list traversal acceleration, Database system, near memory processing, accelerator architectures, memory architecture, Electrical engineering. Electronics. Nuclear engineering, in-memory database, TK1-9971
Description: This paper proposes both software and hardware mechanisms based on the near-memory processing (NMP) accelerator to improve the linked list traversal of the in-memory caching. From a software perspective, we propose a simple but an effective mechanism called ITEM JUMP to reduce the number of traversal on list iteration, and additionally, LSB-first parallel linked list traversal unit, which is an NMP-based hardware accelerator is proposed to improve parallel comparison performance of items. The evaluation result shows LSB-first parallel linked list traversal unit can achieve about 34 times better performance in item comparisons than the case where there is no hardware accelerator, and ITEM JUMP can reduce the number of items retrieved by up to 42%. The proposed NMP-based hardware accelerator also reduces the memory access overhead by 61%–83% compared to a simple parallel linked list traversal unit that simply loads and compares data as fast as possible.
Document Type: Article
ISSN: 2169-3536
DOI: 10.1109/access.2023.3292582
Access URL: https://doaj.org/article/a973790e77264e1f903b733a4c9a3a3b
Rights: CC BY NC ND
Accession Number: edsair.doi.dedup.....2398c9a174c6fd1ff7db88a7531427a1
Database: OpenAIRE
Description
Abstract:This paper proposes both software and hardware mechanisms based on the near-memory processing (NMP) accelerator to improve the linked list traversal of the in-memory caching. From a software perspective, we propose a simple but an effective mechanism called ITEM JUMP to reduce the number of traversal on list iteration, and additionally, LSB-first parallel linked list traversal unit, which is an NMP-based hardware accelerator is proposed to improve parallel comparison performance of items. The evaluation result shows LSB-first parallel linked list traversal unit can achieve about 34 times better performance in item comparisons than the case where there is no hardware accelerator, and ITEM JUMP can reduce the number of items retrieved by up to 42%. The proposed NMP-based hardware accelerator also reduces the memory access overhead by 61%–83% compared to a simple parallel linked list traversal unit that simply loads and compares data as fast as possible.
ISSN:21693536
DOI:10.1109/access.2023.3292582