Govindaraj, V., & Dhanasekar, S. (2024). Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture. IETE Journal of Research, 70, 7513-7525. https://doi.org/10.1080/03772063.2024.2352146
Citace podle Chicago (17th ed.)Govindaraj, V., a S. Dhanasekar. "Test Power Reduction Through Reordering Algorithm Implementation and Advancements in BIST Architecture." IETE Journal of Research 70 (2024): 7513-7525. https://doi.org/10.1080/03772063.2024.2352146.
Citace podle MLA (9th ed.)Govindaraj, V., a S. Dhanasekar. "Test Power Reduction Through Reordering Algorithm Implementation and Advancements in BIST Architecture." IETE Journal of Research, vol. 70, 2024, pp. 7513-7525, https://doi.org/10.1080/03772063.2024.2352146.
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