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Design Of Advanced Encryption Standard (AES) Algorithm Using Verilog

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Název: Design Of Advanced Encryption Standard (AES) Algorithm Using Verilog
Autoři: ATMAKURI KHANDESWARA RAO
Zdroj: International Scientific Journal of Engineering and Management. :1-9
Informace o vydavateli: Indospace Publications, 2025.
Rok vydání: 2025
Popis: Moved Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an embraced cryptographic count that is used to make sure about electronic data. Right now data, need for protection of information is more articulated than any time in recent memory. Secure correspondence is important to protect sensitive data in military and government organizations just as private people. Current encryption gauges are utilized to encode and ensure information during transmission as well as capacity too. This paper offers a technique for combining encrypted and decrypted AES data. This approach may reduce the complexity of the design, particularly in terms of hardware resources required to implement the AES Sub Bytes and Mix columns modules, among other things. AES encryption and decryption are supported by the majority of modules. Moreover, in both encryption and decryption processes, the architecture can still provide a high data rate KEYWORDS: ENCRYPTION, CRYPOTOGRAPHY, MODELSIM, AES, FPGA,VERILOG
Druh dokumentu: Article
ISSN: 2583-6129
DOI: 10.55041/isjem04678
Přístupové číslo: edsair.doi...........4e720cfe8c371231fdbda5caa31bb01c
Databáze: OpenAIRE
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  Data: Moved Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an embraced cryptographic count that is used to make sure about electronic data. Right now data, need for protection of information is more articulated than any time in recent memory. Secure correspondence is important to protect sensitive data in military and government organizations just as private people. Current encryption gauges are utilized to encode and ensure information during transmission as well as capacity too. This paper offers a technique for combining encrypted and decrypted AES data. This approach may reduce the complexity of the design, particularly in terms of hardware resources required to implement the AES Sub Bytes and Mix columns modules, among other things. AES encryption and decryption are supported by the majority of modules. Moreover, in both encryption and decryption processes, the architecture can still provide a high data rate KEYWORDS: ENCRYPTION, CRYPOTOGRAPHY, MODELSIM, AES, FPGA,VERILOG
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