VLSI Implementation of decoding algorithms using EG-LDPC Codes.
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| Title: | VLSI Implementation of decoding algorithms using EG-LDPC Codes. |
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| Authors: | Prasad, M.N. Giri1, Reddy, C. Chinnapu2, Babu, J. Chinna1 jchinnababu@gmail.com |
| Source: | Procedia Computer Science. 2017, Vol. 115, p143-150. 8p. |
| Subject Terms: | Decoding algorithms, Bar codes, Very large scale circuit integration, Parity-check matrix, Parameter estimation |
| Abstract: | The LDPC codes are Shannon Limit codes that can achieve low bit error rates for SNR applications. The features of LDPC Codes are reduction in the decoding time, latency and as well as no error-floors at high SNRs. The proposed algorithms are SBF, MSA, and MLDD. The various decoding algorithms have been compared for these codes. The parameters are describing the which algorithm further helps in selecting the better decoder used for Medical and Signal Processing Applications. These codes are also used in Generating the Barcodes depends on the size of the Parity Check matrix. [ABSTRACT FROM AUTHOR] |
| Database: | Supplemental Index |
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