Olukotun, K., Hammond, L., & Laudon, J. (2007). CHAPTER 4: Improving Latency Using Manual Parallel Programming: 4.2 TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC): MORE GENERALIZED TRANSACTIONAL MEMORY. Chip Multiprocessor Architecture, 116.
Chicago-Zitierstil (17. Ausg.)Olukotun, Kunle, Lance Hammond, und James Laudon. "CHAPTER 4: Improving Latency Using Manual Parallel Programming: 4.2 TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC): MORE GENERALIZED TRANSACTIONAL MEMORY." Chip Multiprocessor Architecture 2007: 116.
MLA-Zitierstil (9. Ausg.)Olukotun, Kunle, et al. "CHAPTER 4: Improving Latency Using Manual Parallel Programming: 4.2 TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC): MORE GENERALIZED TRANSACTIONAL MEMORY." Chip Multiprocessor Architecture, 2007, p. 116.