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Architectural decomposition of video decoders for many core architectures.

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Názov: Architectural decomposition of video decoders for many core architectures.
Autori: Richter, Henryk, Stabernack, Benno, Kuhn, Volker
Zdroj: Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing; 1/ 1/2012, p1-8, 8p
Abstrakt: The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. In video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource allocation/synchronization for multiple threads. In this paper, we propose a decoder architecture that replaces the conventional monolithic design with a pipelined structure. Bit stream decoding and image processing are separated from each other by means of a Meta Format Stream. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264 multiprocessing proposal is presented as a case study for the potential our our decoder architecture. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage. The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution. [ABSTRACT FROM PUBLISHER]
Copyright of Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Architectural decomposition of video decoders for many core architectures.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Richter%2C+Henryk%22">Richter, Henryk</searchLink><br /><searchLink fieldCode="AR" term="%22Stabernack%2C+Benno%22">Stabernack, Benno</searchLink><br /><searchLink fieldCode="AR" term="%22Kuhn%2C+Volker%22">Kuhn, Volker</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing; 1/ 1/2012, p1-8, 8p
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. In video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource allocation/synchronization for multiple threads. In this paper, we propose a decoder architecture that replaces the conventional monolithic design with a pipelined structure. Bit stream decoding and image processing are separated from each other by means of a Meta Format Stream. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264 multiprocessing proposal is presented as a case study for the potential our our decoder architecture. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage. The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution. [ABSTRACT FROM PUBLISHER]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 8
        StartPage: 1
    Titles:
      – TitleFull: Architectural decomposition of video decoders for many core architectures.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Richter, Henryk
      – PersonEntity:
          Name:
            NameFull: Stabernack, Benno
      – PersonEntity:
          Name:
            NameFull: Kuhn, Volker
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 01
              Text: 1/ 1/2012
              Type: published
              Y: 2012
          Identifiers:
            – Type: isbn-print
              Value: 9781467320894
          Titles:
            – TitleFull: Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing
              Type: main
ResultId 1