Liu, Q., Constantinides, G. A., Masselos, K., & Cheung, P. Y. K. (2009). Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 28(3), 305-315. https://doi.org/10.1109/TCAD.2009.2013541
Chicago-Zitierstil (17. Ausg.)Liu, Qiang, George A. Constantinides, Konstantinos Masselos, und Peter Y. K. Cheung. "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework." IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 28, no. 3 (2009): 305-315. https://doi.org/10.1109/TCAD.2009.2013541.
MLA-Zitierstil (9. Ausg.)Liu, Qiang, et al. "Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework." IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 28, no. 3, 2009, pp. 305-315, https://doi.org/10.1109/TCAD.2009.2013541.