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x2DL: A high throughput architecture for binary‐ring‐learning‐with‐error‐based post quantum cryptography schemes.

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Titel: x2DL: A high throughput architecture for binary‐ring‐learning‐with‐error‐based post quantum cryptography schemes.
Autoren: Ahmadunnisa, Shaik, Mathe, Sudha Ellison
Quelle: IET Quantum Communication; Dec2024, Vol. 5 Issue 4, p349-359, 11p
Schlagwörter: LATTICE theory, CRYPTOGRAPHY, COMPUTER input-output equipment, POLYNOMIALS
Abstract: Lattice‐based cryptography is one of the most promising cryptographic scheme which lies on the hardness of ring‐learning‐with‐error (RLWE). A new variant of RLWE, known as binary‐ring‐learning‐with‐error (BRLWE), has less key size and more efficient hardware implementations compared to RLWE‐based schemes. The key arithmetic operation for BRLWE‐based encryption scheme is the implementation of arithmetic operation represented by FD+H $FD+H$, where both F $F$ and H $H$ are integer polynomials, and D $D$ is a binary polynomial. An efficient architecture to perform the arithmetic operation FD+H $FD+H$ over a polynomial ring xn+1 ${x}^{n}+1$ is proposed. We employ two linear feedback shift register structures comprising x2 ${x}^{2}$‐net units in our design to reduce the computational time. This reduction in computational time yields to a significant improvement in the other performance metrics such as delay, area‐delay product (ADP), power‐delay product, throughput and efficiency compared to the existing designs. As per the experimental results, the authors' proposed design has 32% $32\%$ improvement in ADP when compared to the recently reported work. [ABSTRACT FROM AUTHOR]
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Abstract:Lattice‐based cryptography is one of the most promising cryptographic scheme which lies on the hardness of ring‐learning‐with‐error (RLWE). A new variant of RLWE, known as binary‐ring‐learning‐with‐error (BRLWE), has less key size and more efficient hardware implementations compared to RLWE‐based schemes. The key arithmetic operation for BRLWE‐based encryption scheme is the implementation of arithmetic operation represented by FD+H $FD+H$, where both F $F$ and H $H$ are integer polynomials, and D $D$ is a binary polynomial. An efficient architecture to perform the arithmetic operation FD+H $FD+H$ over a polynomial ring xn+1 ${x}^{n}+1$ is proposed. We employ two linear feedback shift register structures comprising x2 ${x}^{2}$‐net units in our design to reduce the computational time. This reduction in computational time yields to a significant improvement in the other performance metrics such as delay, area‐delay product (ADP), power‐delay product, throughput and efficiency compared to the existing designs. As per the experimental results, the authors' proposed design has 32% $32\%$ improvement in ADP when compared to the recently reported work. [ABSTRACT FROM AUTHOR]
ISSN:26328925
DOI:10.1049/qtc2.12110