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Scalable Processor Instruction Set Extension.

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Titel: Scalable Processor Instruction Set Extension.
Autoren: Becker, Jürgen, Thomas, Alexander
Quelle: IEEE Design & Test of Computers; Mar/Apr2005, Vol. 22 Issue 2, p136-148, 13p, 2 Black and White Photographs, 9 Diagrams, 2 Charts, 1 Graph
Schlagwörter: MICROPROCESSORS, ADAPTIVE computing systems, COMPUTER systems, MPEG (Video coding standard), COMPUTER architecture
Abstract: Explores the integration of the general-purpose, SPARC-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. Goal of the integration of optimizing the execution of complex multimedia applications such as MPEG-4; Benefits of the processor concept; Optimization of customized microprocessors or ASIC; Basis of the XPP architecture.
Datenbank: Complementary Index
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  Data: IEEE Design & Test of Computers; Mar/Apr2005, Vol. 22 Issue 2, p136-148, 13p, 2 Black and White Photographs, 9 Diagrams, 2 Charts, 1 Graph
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  Data: Explores the integration of the general-purpose, SPARC-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. Goal of the integration of optimizing the execution of complex multimedia applications such as MPEG-4; Benefits of the processor concept; Optimization of customized microprocessors or ASIC; Basis of the XPP architecture.
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        Value: 10.1109/MDT.2005.43
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        Text: English
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        PageCount: 13
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      – SubjectFull: ADAPTIVE computing systems
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              Text: Mar/Apr2005
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