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PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow.

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Title: PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow.
Authors: Huang, Sitao, Wu, Kun, Jeong, Hyunmin, Wang, Chengyue, Chen, Deming, Hwu, Wen-Mei
Source: IEEE Transactions on Computers; Dec2021, Vol. 70 Issue 12, p2015-2028, 14p
Subject Terms: PYTHON programming language, FIELD programmable gate arrays, ALGORITHMS
Abstract: The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms such as FPGAs. However, a high-quality FPGA design is very hard to create and optimize as it requires FPGA expertise and a long design iteration time. In contrast, software applications are typically developed in a short development cycle, with high-level languages like Python, which have much higher levels of abstraction than all existing hardware design flows. To close this gap between hardware design flows and software applications, and simplify FPGA programming, we create PyLog, a high-level, algorithm-centric Python-based programming and synthesis flow for FPGA. PyLog is powered by a set of compiler optimization passes and a type inference system to generate high-quality hardware design. It abstracts away the implementation details, and allows designers to focus on algorithm specification. PyLog takes in Python functions, generates PyLog intermediate representation (PyLog IR), performs several optimization passes, including pragma insertion, design space exploration, and memory customization, etc., and creates complete FPGA system designs. PyLog also has a runtime that allows users to run the PyLog code directly on the target FPGA platform without any extra code development. The whole design flow is automated. Evaluation shows that PyLog significantly improves FPGA design productivity and generates highly efficient FPGA designs that outperform highly optimized CPU implementation and state-of-the-art FPGA implementation by $3.17\times$ 3. 17 × and $1.24\times$ 1. 24 × on average. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow.
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  Data: <searchLink fieldCode="AR" term="%22Huang%2C+Sitao%22">Huang, Sitao</searchLink><br /><searchLink fieldCode="AR" term="%22Wu%2C+Kun%22">Wu, Kun</searchLink><br /><searchLink fieldCode="AR" term="%22Jeong%2C+Hyunmin%22">Jeong, Hyunmin</searchLink><br /><searchLink fieldCode="AR" term="%22Wang%2C+Chengyue%22">Wang, Chengyue</searchLink><br /><searchLink fieldCode="AR" term="%22Chen%2C+Deming%22">Chen, Deming</searchLink><br /><searchLink fieldCode="AR" term="%22Hwu%2C+Wen-Mei%22">Hwu, Wen-Mei</searchLink>
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  Data: IEEE Transactions on Computers; Dec2021, Vol. 70 Issue 12, p2015-2028, 14p
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  Data: <searchLink fieldCode="DE" term="%22PYTHON+programming+language%22">PYTHON programming language</searchLink><br /><searchLink fieldCode="DE" term="%22FIELD+programmable+gate+arrays%22">FIELD programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22ALGORITHMS%22">ALGORITHMS</searchLink>
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  Data: The exploding complexity and computation efficiency requirements of applications are stimulating a strong demand for hardware acceleration with heterogeneous platforms such as FPGAs. However, a high-quality FPGA design is very hard to create and optimize as it requires FPGA expertise and a long design iteration time. In contrast, software applications are typically developed in a short development cycle, with high-level languages like Python, which have much higher levels of abstraction than all existing hardware design flows. To close this gap between hardware design flows and software applications, and simplify FPGA programming, we create PyLog, a high-level, algorithm-centric Python-based programming and synthesis flow for FPGA. PyLog is powered by a set of compiler optimization passes and a type inference system to generate high-quality hardware design. It abstracts away the implementation details, and allows designers to focus on algorithm specification. PyLog takes in Python functions, generates PyLog intermediate representation (PyLog IR), performs several optimization passes, including pragma insertion, design space exploration, and memory customization, etc., and creates complete FPGA system designs. PyLog also has a runtime that allows users to run the PyLog code directly on the target FPGA platform without any extra code development. The whole design flow is automated. Evaluation shows that PyLog significantly improves FPGA design productivity and generates highly efficient FPGA designs that outperform highly optimized CPU implementation and state-of-the-art FPGA implementation by $3.17\times$ 3. 17 × and $1.24\times$ 1. 24 × on average. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Computers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TC.2021.3123465
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      – Code: eng
        Text: English
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        PageCount: 14
        StartPage: 2015
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        Type: general
      – SubjectFull: FIELD programmable gate arrays
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      – SubjectFull: ALGORITHMS
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              Text: Dec2021
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