Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU.
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| Title: | Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU. |
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| Authors: | Wang, Biao1 biaowang@win.tu-berlin.de, de Souza, Diego Felix2, Alvarez-Mesa, Mauricio3, Chi, Chi Ching3, Juurlink, Ben1, Ilić, Aleksandar2, Roma, Nuno2, Sousa, Leonel2 |
| Source: | Signal Processing: Image Communication. Mar2018, Vol. 62, p93-105. 13p. |
| Subject Terms: | *VIDEO coding, *CENTRAL processing units, *GRAPHICS processing units, *VIDEO compression, *ENERGY consumption |
| Abstract: | The High Efficiency Video Coding HEVC standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units GPU are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of 2 . 2 × . When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU. [ABSTRACT FROM AUTHOR] |
| Database: | Academic Search Index |
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| Header | DbId: asx DbLabel: Academic Search Index An: 128044489 RelevancyScore: 1243 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 1243.43908691406 |
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| Items | – Name: Title Label: Title Group: Ti Data: Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wang%2C+Biao%22">Wang, Biao</searchLink><relatesTo>1</relatesTo><i> biaowang@win.tu-berlin.de</i><br /><searchLink fieldCode="AR" term="%22de+Souza%2C+Diego+Felix%22">de Souza, Diego Felix</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Alvarez-Mesa%2C+Mauricio%22">Alvarez-Mesa, Mauricio</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Chi%2C+Chi+Ching%22">Chi, Chi Ching</searchLink><relatesTo>3</relatesTo><br /><searchLink fieldCode="AR" term="%22Juurlink%2C+Ben%22">Juurlink, Ben</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Ilić%2C+Aleksandar%22">Ilić, Aleksandar</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Roma%2C+Nuno%22">Roma, Nuno</searchLink><relatesTo>2</relatesTo><br /><searchLink fieldCode="AR" term="%22Sousa%2C+Leonel%22">Sousa, Leonel</searchLink><relatesTo>2</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Signal+Processing%3A+Image+Communication%22">Signal Processing: Image Communication</searchLink>. Mar2018, Vol. 62, p93-105. 13p. – Name: Subject Label: Subject Terms Group: Su Data: *<searchLink fieldCode="DE" term="%22VIDEO+coding%22">VIDEO coding</searchLink><br />*<searchLink fieldCode="DE" term="%22CENTRAL+processing+units%22">CENTRAL processing units</searchLink><br />*<searchLink fieldCode="DE" term="%22GRAPHICS+processing+units%22">GRAPHICS processing units</searchLink><br />*<searchLink fieldCode="DE" term="%22VIDEO+compression%22">VIDEO compression</searchLink><br />*<searchLink fieldCode="DE" term="%22ENERGY+consumption%22">ENERGY consumption</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: The High Efficiency Video Coding HEVC standard provides a higher compression efficiency than other video coding standards but at the cost of an increased computational load, which makes hard to achieve real-time encoding/decoding for ultra high-resolution and high-quality video sequences. Graphics Processing Units GPU are known to provide massive processing capability for highly parallel and regular computing kernels, but not all HEVC decoding procedures are suited for GPU execution. Furthermore, if HEVC decoding is accelerated by GPUs, energy efficiency is another concern for heterogeneous CPU+GPU decoding. In this paper, a highly parallel HEVC decoder for heterogeneous CPU+GPU system is proposed. It exploits available parallelism in HEVC decoding on the CPU, GPU, and between the CPU and GPU devices simultaneously. On top of that, different workload balancing schemes can be selected according to the devoted CPU and GPU computing resources. Furthermore, an energy optimized solution is proposed by tuning GPU clock rates. Results show that the proposed decoder achieves better performance than the state-of-the-art CPU decoder, and the best performance among the workload balancing schemes depends on the available CPU and GPU computing resources. In particular, with an NVIDIA Titan X Maxwell GPU and an Intel Xeon E5-2699v3 CPU, the proposed decoder delivers 167 frames per second (fps) for Ultra HD 4K videos, when four CPU cores are used. Compared to the state-of-the-art CPU decoder using four CPU cores, the proposed decoder gains a speedup factor of 2 . 2 × . When decoding performance is bounded by the CPU, a system wise energy reduction up to 36% is achieved by using fixed (and lower) GPU clocks, compared to the default dynamic clock settings on the GPU. [ABSTRACT FROM AUTHOR] |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1016/j.image.2017.12.009 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 93 Subjects: – SubjectFull: VIDEO coding Type: general – SubjectFull: CENTRAL processing units Type: general – SubjectFull: GRAPHICS processing units Type: general – SubjectFull: VIDEO compression Type: general – SubjectFull: ENERGY consumption Type: general Titles: – TitleFull: Highly parallel HEVC decoding for heterogeneous systems with CPU and GPU. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wang, Biao – PersonEntity: Name: NameFull: de Souza, Diego Felix – PersonEntity: Name: NameFull: Alvarez-Mesa, Mauricio – PersonEntity: Name: NameFull: Chi, Chi Ching – PersonEntity: Name: NameFull: Juurlink, Ben – PersonEntity: Name: NameFull: Ilić, Aleksandar – PersonEntity: Name: NameFull: Roma, Nuno – PersonEntity: Name: NameFull: Sousa, Leonel IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 03 Text: Mar2018 Type: published Y: 2018 Identifiers: – Type: issn-print Value: 09235965 Numbering: – Type: volume Value: 62 Titles: – TitleFull: Signal Processing: Image Communication Type: main |
| ResultId | 1 |
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