Výsledky vyhľadávania - width-partitioned microarchitecture

A case for a complexity-effective, width-partitioned microarchitecture

Autori: Olivier Rochecouste André Seznec Gilles Pokam

Zdroj: ACM Transactions on Architecture and Code Optimization. 3:295-326

Predmety: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Prístupová URL adresa: http://dl.acm.org/ft_gateway.cfm?id=1162693&type=pdf
https://hal.inria.fr/inria-00000211/document
https://dblp.uni-trier.de/db/journals/taco/taco3.html#RochecoustePS06
https://hal.inria.fr/inria-00070336
https://dl.acm.org/doi/10.1145/1162690.1162693
https://dl.acm.org/doi/pdf/10.1145/1162690.1162693

A Case for a Complexity-Effective, Width-partitioned Microarchitecture

Autori: Rochecouste, Olivier Pokam, Gilles Seznec, André a ďalší

Prispievatelia: Rochecouste, Olivier Pokam, Gilles Seznec, André a ďalší

Predmety: fichier de registres, data-width predictor \\ Complexité matérielle, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], narrow-width operations, POWER CONSUMPTION, consommation électrique, superscalar processor, Hardaware complexity, power consumption, DATA-WIDTH PREDICTOR, [INFO.INFO-OH] Computer Science [cs]/Other [cs.OH], prédicteur de largeur, width-partitioned microarchitecture, SUPERSCALAR PROCESSOR, WIDTH-PARTITIONED MICROARCHITECTURE, microarchitecture clusterisée, HARDWARE COMPLEXITY, processeur superscalaire, register file, REGISTER FILE, NARROW-WIDTH OPERATIONS, opérations tronquées

Popis súboru: application/pdf

Prístupová URL adresa: https://inria.hal.science/inria-00000211v1
https://inria.hal.science/inria-00070336v1

A case for a complexity-effective, width-partitioned microarchitecture.

Autori: Rochecouste, Olivier Pokam, Gilles Seznec, André

Zdroj: ACM Transactions on Architecture & Code Optimization; Sep2006, Vol. 3 Issue 3, p295-326, 32p

CHAPTER 4: Optimizing Capacitance and Switching Activity to Reduce Dynamic Power: 4.13 DYNAMIC WORK STEERING.

Autori: Kaxiras, Stefanos Martonosi, Margaret

Zdroj: Computer Architecture Techniques for Power-Efficiency; 2008, p124-129, 6p

A survey of value prediction techniques for leveraging value locality.

Autori: Mittal, Sparsh

Zdroj: Concurrency & Computation: Practice & Experience; 11/10/2017, Vol. 29 Issue 21, pn/a-N.PAG, 24p

Predmety: COMPUTER storage capacity, BANDWIDTH allocation, COMPUTER scheduling, COMPUTER architecture, INTEGRATED circuits

Characterizing and Exploiting Small-Value Memory Instructions.

Autori: Islam, Mafijul Md. Stenstrom, Per

Zdroj: IEEE Transactions on Computers; Jul2014, Vol. 63 Issue 7, p1640-1655, 16p

Predmety: COMPUTER storage capacity, APPLICATION software, PERSONAL computers, COMPUTER software execution, ENERGY dissipation, STATIC VAR compensators, COMPUTER memory management

Dissecting Computer Architecture

Autori: Albuero De Luna, Alvin

Typ zdroja: eBook.

Predmet: Computer architecture

Kategórie: COMPUTERS / Computer Architecture

Computer Architecture Techniques for Power-Efficiency

Autori: Stefanos Kaxiras Margaret Martonosi

Typ zdroja: eBook.

Predmet: Electronic circuits, Microprocessors, Computer architecture

Kategórie: TECHNOLOGY & ENGINEERING / Electronics / Circuits / General, COMPUTERS / Computer Architecture