Search Results - variable-bins high efficiency video coding CABAC decoder

Field programmable gate array implementation of variable‐bins high efficiency video coding CABAC decoder with path delay optimisation

Authors: Wahiba Menasri Abdellah Skoudarli Aichouche Belhadj et al.

Source: IET Image Processing. 13:954-963

Subject Terms: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Access URL: https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-ipr.2018.6336
https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2018.6336
https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-ipr.2018.6336
https://dblp.uni-trier.de/db/journals/iet-ipr/iet-ipr13.html#MenasriSBA19
https://doi.org/10.1049/iet-ipr.2018.6336

Field programmable gate array implementation of variable‐bins high efficiency video coding CABAC decoder with path delay optimisation.

Authors: Menasri, Wahiba Skoudarli, Abdellah Belhadj, Aichouche et al.

Source: IET Image Processing (Wiley-Blackwell); May2019, Vol. 13 Issue 6, p954-963, 10p

Design and FPGA implementation of mixed VVC/HEVC CABAC decoding.

Authors: Menasri, Wahiba Morsli, Abdelkader Skoudarli, Abdallah et al.

Source: Signal, Image & Video Processing; Aug2024, Vol. 18 Issue 6/7, p5401-5412, 12p

Performance comparison of throughput between AVC, HEVC and VVC hardware CABAC decoder.

Authors: Menasri, Wahiba Skoudarli, Abdellah

Source: Journal of Real-Time Image Processing; Apr2023, Vol. 20 Issue 2, p1-12, 12p

A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications.

Authors: Chen, Yu-Hsin Sze, Vivienne

Source: IEEE Transactions on Circuits & Systems for Video Technology; May2015, Vol. 25 Issue 5, p856-868, 13p

Subject Terms: VIDEO coding, DATA pipelining, BINARY codes, STANDARDIZATION, FINITE state machines

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder.

Authors: Liao, Yuan-Hsin Li, Gwo-Long Chang, Tian-Sheuan

Source: IEEE Transactions on Circuits & Systems for Video Technology; Feb2012, Vol. 22 Issue 2, p272-281, 10p

Subject Terms: VIDEO coding, DECODING algorithms, HIGH definition television, DATA pipelining, BIT rate

Image and Video Coding Techniques for Ultra-low Latency.

Authors: ŽÁDNÍK, JAKUB MÄKITALO, MARKKU VANNE, JARNO et al.

Source: ACM Computing Surveys; 2022 Suppl 11, Vol. 54, p1-35, 35p

Subject Terms: VIDEO coding, IMAGE compression, NEXT generation networks, AUTONOMOUS vehicles

Double bit range estimation with eight estimators for CABAC in VVC.

Authors: Chan, Ka‐Hou Im, Sio‐Kei

Source: IET Image Processing (Wiley-Blackwell); Oct2022, Vol. 16 Issue 12, p3155-3163, 9p

Subject Terms: BINARY codes, ARITHMETIC, ENTROPY, SCALABILITY, PROBABILITY theory, CHANNEL coding

High Efficiency Video Coding (HEVC) : Algorithms and Architectures

Authors: Vivienne Sze Madhukar Budagavi Gary J. Sullivan

Resource Type: eBook.

Subjects: Computer graphics, Engineering, Digital video--Standards, Video compression--Standards, Systems engineering

Categories: TECHNOLOGY & ENGINEERING / Signals & Signal Processing, COMPUTERS / Software Development & Engineering / Computer Graphics, TECHNOLOGY & ENGINEERING / Electronics / Circuits / General

An improved symbol reduction technique based Huffman coder for efficient entropy coding in the transform coders.

Authors: Thakur, Vikrant Singh Thakur, Kavita Gupta, Shubhrata

Source: IET Image Processing (Wiley-Blackwell); Mar2021, Vol. 15 Issue 4, p1008-1022, 15p

Reconfigurable architecture for entropy decoding and inverse transform in H.264.

Authors: Lo, Chia-Cheng Tsai, Shang-Ta Shieh, Ming-Der

Source: IEEE Transactions on Consumer Electronics; Aug2010, Vol. 56 Issue 3, p1670-1676, 0p

Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding.

Authors: Peng Zhang Don Xie Wen Gao

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Mar2009, Vol. 17 Issue 3, p417-426, 10p, 3 Black and White Photographs, 3 Charts, 10 Graphs

Subject Terms: VERY large scale circuit integration, DECODERS & decoding, INTEGRATED circuits, DECODERS (Electronics), EMBEDDED computer systems, SYSTEMS design

Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders.

Authors: Pastuszak, Grzegorz

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Dec2020, Vol. 28 Issue 12, p2573-2583, 11p

Subject Terms: ENTROPY, VIDEO compression, STREAMING media, GATE array circuits, BINARY codes

A Novel Parallel Pipeline Structure of VP9 Decoder.

Authors: Huabiao Qin Wu Chen Sijun Yi et al.

Source: Proceedings of SPIE; 2018, Vol. 10615, p1-6, 6p

Optimal FPGA memory allocation for image processing.

Authors: Bao, Bengang Liang, Xiaoling

Source: Journal of Computational Methods in Sciences & Engineering; 2023, Vol. 23 Issue 4, p1801-1814, 14p

Subject Terms: IMAGE processing, FIELD programmable gate arrays, PARALLEL algorithms, COMPUTER vision, VISUAL fields, DIGITAL image processing

Decoder Hardware Architecture for HEVC.

Authors: Tikekar, Mehul Huang, Chao-Tsung Juvekar, Chiraag et al.

Source: High Efficiency Video Coding (HEVC); 2014, p303-341, 39p

INTEGRATED IMAGE RESHAPING AND VIDEO CODING

Integrated image reshaping and video coding

INTEGRATED IMAGE RESHAPING AND VIDEO CODING

Integrated image reshaping and video coding