Suchergebnisse - unified encryption/decryption architecture

A high performance ST-Box based unified AES encryption/decryption architecture on FPGA

Autoren: Arshad Aziz Dur-e-Shahwar Kundi Nassar Ikram

Quelle: Microprocessors and Microsystems. 41:37-46

Schlagwörter: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: https://www.sciencedirect.com/science/article/pii/S0141933115001945
http://www.sciencedirect.com/science/article/pii/S0141933115001945
https://dblp.uni-trier.de/db/journals/mam/mam41.html#KundiAI16

A Privacy-Preserving Polymorphic Heterogeneous Security Architecture for Cloud–Edge Collaboration Industrial Control Systems.

Autoren: Niu, Yukun Han, Xiaopeng He, Chuan et al.

Quelle: Applied Sciences (2076-3417); Jul2025, Vol. 15 Issue 14, p8032, 30p

Schlagwörter: DATA protection, SECURITY management, REDUNDANCY in engineering, INDUSTRIAL controls manufacturing, SCHEDULING, DISTRIBUTED computing

A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl

Autoren: At, Nuray Beuchat, Jean-Luc Okamoto, Eiji et al.

Weitere Verfasser: At, Nuray Beuchat, Jean-Luc Okamoto, Eiji et al.

Quelle: Journal of Parallel and Distributed Computing. 106:106-120

Schlagwörter: Coprocessors, Field Programmable Gate Arrays, Ciphers, 0103 physical sciences, Cryptography, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Embedded Systems, Cryptographic Hash Functions, 01 natural sciences

Dateibeschreibung: application/pdf

Zugangs-URL: http://eprint.iacr.org/2012/535.pdf
https://earsiv.anadolu.edu.tr/xmlui/handle/11421/20272
https://www.sciencedirect.com/science/article/pii/S0743731517300485
https://dblp.uni-trier.de/db/journals/jpdc/jpdc106.html#AtBOSY17
https://jglobal.jst.go.jp/detail?JGLOBAL_ID=201802282225448252

Distributed satellite information networks: architecture, enabling technologies, and trends.

Autoren: Zhang, Qinyu Xu, Liang Huang, Jianhao et al.

Quelle: SCIENCE CHINA Information Sciences; Sep2025, Vol. 68 Issue 9, p1-73, 73p

A Flexible Architecture for Cryptographic Applications: ECC and PRESENT.

Autoren: Rashid, Muhammad Sonbul, Omar S. Arif, Muhammad et al.

Quelle: Computers, Materials & Continua; 2023, Vol. 76 Issue 1, p1009-1025, 17p

Schlagwörter: BLOCK ciphers, DATA encryption, MULTIPLICATION, CRYPTOGRAPHY

UniStream: A unified stream architecture combining configuration and data processing

Autoren: Jian Yan Jifang Jin Lingli Wang et al.

Quelle: 2015 25th International Conference on Field Programmable Logic and Applications (FPL). :1-4

Schlagwörter: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Zugangs-URL: http://ieeexplore.ieee.org/document/7294000/
http://dblp.uni-trier.de/db/conf/fpl/fpl2015.html#YanJWZLW15
https://dblp.uni-trier.de/db/conf/fpl/fpl2015.html#YanJWZLW15

A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl

Autoren: Marcin Rogawski Kris Gaj Ekawat Homsirikamol

Quelle: Microprocessors and Microsystems. 37:572-582

Schlagwörter: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Zugangs-URL: https://dl.acm.org/doi/10.1016/j.micpro.2013.05.005
https://dblp.uni-trier.de/db/journals/mam/mam37.html#RogawskiGH13
https://www.sciencedirect.com/science/article/pii/S0141933113000847

FPGA-based implementation of an S-Box cryptographic co-processor for high-performance applications.

Autoren: Nassim, Moulai Khatir Ahmed Zakarya, Ziani

Quelle: Indonesian Journal of Electrical Engineering & Computer Science; Nov2025, Vol. 40 Issue 2, p1167-1176, 10p

A low-area unified hardware architecture for the AES and the cryptographic hash function ECHO

Autoren: Jean-Luc Beuchat Eiji Okamoto Teppei Yamazaki

Quelle: Journal of Cryptographic Engineering. 1:101-121

Schlagwörter: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Zugangs-URL: http://eprint.iacr.org/2012/535.pdf
https://dblp.uni-trier.de/db/journals/jce/jce1.html#BeuchatOY11
https://link.springer.com/article/10.1007%2Fs13389-011-0009-8

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication.

Autoren: Su, Yang Yang, Bai-Long Yang, Chen et al.

Quelle: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Aug2022, Vol. 30 Issue 8, p993-1006, 14p

Schlagwörter: DIGITAL signal processing, MULTIPLICATION, POLYNOMIALS, FIELD programmable gate arrays, GATE array circuits

Post-quantum-inspired scalable blockchain architecture for internet hospital systems with lightweight privacy-preserving access control.

Autoren: Hao, Lulu Wang, Ruoyu Wang, Xiaofeng et al.

Quelle: PLoS ONE; 12/1/2025, Vol. 20 Issue 12, p1-33, 33p

Schlagwörter: BLOCKCHAINS, ACCESS control, CRYPTOGRAPHY, TELEMEDICINE, INTERNET of medical things, DATA management, DATA protection

A novel FPGA-based hybrid cryptographic architecture integrating hummingbird and PRESENT ciphers with signal processing techniques for enhanced security in resource-constrained IoT devices.

Autoren: Parthiban, V. Raja, J.

Quelle: Analog Integrated Circuits & Signal Processing; Oct2025, Vol. 125 Issue 1, p1-22, 22p

A unified data collection framework based on the data plane for 6G.

Alternate Title: 一种基于6G数据面的统一数据收集框架. (Chinese)

Autoren: Yuan, Yannan Qin, Fei Liu, Jiankang et al.

Quelle: Frontiers of Information Technology & Electronic Engineering; Feb2025, Vol. 26 Issue 2, p293-300, 8p

Fully Synthesizable Unified True Random Number Generator and Cryptographic Core.

Autoren: Taneja, Sachin Alioto, Massimo

Quelle: IEEE Journal of Solid-State Circuits; Oct2021, Vol. 56 Issue 10, p3049-3061, 13p

Schlagwörter: RANDOM number generators, RANDOM numbers, COMPLEMENTARY metal oxide semiconductors, CRYPTOGRAPHY, COMPUTER architecture

Resilient security architecture for smart buildings using DLT powered encryption.

Autoren: Priyadarshini, Ishaani Puri, Vikram Kataria, Aman et al.

Quelle: Scientific Reports; 11/27/2025, Vol. 15 Issue 1, p1-17, 17p

Schlagwörter: DATA encryption, SENSOR networks, BLOCKCHAINS, DATA transmission systems, BUILT environment, INTELLIGENT buildings

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.

Autoren: Ueno, Rei Homma, Naofumi Morioka, Sumio et al.

Quelle: IEEE Transactions on Computers; Apr2020, Vol. 69 Issue 4, p534-548, 15p

Schlagwörter: ADVANCED Encryption Standard, LOGIC design, LINEAR operators, BLOCK ciphers, IMAGE encryption

Towards a secure cloud repository architecture for the continuous monitoring of patients with mental disorders.

Autoren: Georgiou, Dimitra Katsaounis, Stamatis Tsanakas, Panayiotis et al.

Quelle: Frontiers in Digital Health; 2025, p1-17, 17p

Schlagwörter: DATA security, COMPUTER software, RESEARCH funding, MENTAL illness, PRIVACY, WEARABLE technology, BIOMETRY, CONCEPTUAL structures, PATIENT monitoring, MANAGEMENT of medical records, WIRELESS LANs, MEDICAL ethics

Consensus-Driven Blockchain Authentication for Resilient Healthcare IoT Applications.

Autoren: Sharma, Geeta Dhiman, Vikram Kumar, Mukesh et al.

Quelle: International Journal of Networked & Distributed Computing; Dec2025, Vol. 13 Issue 2, p1-21, 21p

Polynomial inversion hardware accelerator for post quantum algorithm.

Autoren: Divya, B Raja Sekar, K David Selvakumar, A et al.

Quelle: Sādhanā: Academy Proceedings in Engineering Sciences; Dec2025, Vol. 50 Issue 4, p1-14, 14p

Schlagwörter: CRYPTOGRAPHY, POLYNOMIALS, ALGORITHMS, PROGRAMMABLE logic devices, COMPUTATIONAL complexity, OPTIMIZATION algorithms

High-Performance Multi-RNS-Assisted Concurrent RSA Cryptosystem Architectures.

Autoren: Elango, S. Sampath, P. Raja Sekar, S. et al.

Quelle: Journal of Circuits, Systems & Computers; Oct2023, Vol. 32 Issue 15, p1-25, 25p

Schlagwörter: RSA algorithm, PUBLIC key cryptography, APPLICATION-specific integrated circuits, MODULAR arithmetic, NUMBER systems

Firma/Körperschaft: TAIWAN Semiconductor Manufacturing Co. Ltd.