Search Results - types AND design styles—(gate OR game) arrays general terms algorithms
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Source: Technologies (2227-7080); Aug2025, Vol. 13 Issue 8, p321, 15p
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Source: Asia-Pacific Journal of Operational Research; Dec2024, Vol. 41 Issue 6, p1-29, 29p
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Subject Terms: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays General Terms Algorithms, Performance, Design, Experimentation Keywords FPGA, Technology Mapping, Cut Enumeration, Area Flow, Edge Flow
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.299.5175; http://www.eecs.berkeley.edu/~alanmi/publications/2008/fpga08_wmap.pdf
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Source: Sensors (14248220); Dec2023, Vol. 23 Issue 23, p9495, 21p
Subject Terms: EDGE computing, ARTIFICIAL intelligence, PROCESS capability, INTERNET of things, ALGORITHMS
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Source: Proceedings of the Annual Meeting of the United States Animal Health Association. 10/10/2024, Vol. 128, p1-339. 336p.
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Source: Veterinary Evidence. Jul-Sep2025, Vol. 10 Issue 3, p1-31. 31p.
Subjects: Veterinary medicine, Ethics, Biology, Pragmatism, Worldview, Practice of veterinary medicine, Historical source material
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Source: Veterinary Sciences. Dec2024, Vol. 11 Issue 12, p627. 30p.
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Source: Veterinary Sciences. Sep2023, Vol. 10 Issue 9, p537. 25p.
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Source: Journal of Animal Ecology. Jul2024, Vol. 93 Issue 7, p876-890. 15p.
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Source: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/glsvlsi04/pdffiles/p348.pdf.
Subject Terms: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate Arrays General Terms Algorithms, Design Keywords SPFD, Logic Optimization, One-to-Many Rewiring (OMR
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Subject Terms: Categories and Subject Descriptors D.3.4 [Compilers, Parallelizing Compilers, B.5.2 [Designs Aids, Automatic Synthesis, D.7.1 [Types and Design Styles, Algorithms implemented in hardware, Gate Arrays General Terms Algorithms, Performance, Design, Experimentation Keywords Design Space Exploration, Data Dependence Analysis, Reuse Analysis, Loop Transformations
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.1833; http://www.ece.ucsb.edu/~kastner/ece253/reader/so02.pdf
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Subject Terms: Categories and Subject Descriptors B.3.2 [Memory Structures, Design Styles—Associative Memories, B.7.1 [Integrated Circuits, Types and Design Styles—Gate Arrays, E.2 [Data, Data Storage Representations—Hash-table representations General Terms Algorithms, Design, Performance Keywords FPGA, BRAM, Associative Memory, CAM, Cache, Hashing
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.366.3876; http://ic.ese.upenn.edu/pdf/dmhc_fpga2013.pdf
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Subject Terms: Categories and Subject Descriptors, D.3.4 [Programming Languages, Processors—Code generation, Compilers, Optimization, C.1.3 [Processor Architectures, Other Architecture Styles—Adaptable architectures, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Languages, Performance Additional Key Words and Phrases, Instr
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.81.6354; http://ce.et.tudelft.nl/publicationfiles/1140_7_MoscuTecs.pdf
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Subject Terms: Categories and Subject Descriptors, B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays General Terms, Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases, FPGA, technology mapping, cut enumeration, area flow, edge flow
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.127; http://www.eecs.berkeley.edu/~alanmi/publications/2009/trets09_wmap.pdf
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Source: http://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/2004/fpga04/pdffiles/p099.pdf.
Subject Terms: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids – Automatic synthesis, Optimization, B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays, B.7.2 [Integrated Circuits, Design Aids – Layout, Placement and routing, B.8.2 [Performance and Reliability, Performance Analysis and Design Aids. General Terms Algorithms, Performance, Design. Keywords FPGA, Logic synthesis, Placement, Timing Optimization
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Subject Terms: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles—Gate ar- rays, B.7.2 [Integrated Circuits, Design Aids—Placement and routing, D.1.3 [Programming Techniques, Concurrent Program- ming—Distributed programming General Terms Algorithms, Performance, Design Keywords Parallel placement, FPGAs, Timing-driven placement, Analytical
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Subject Terms: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles – Gate arrays, Advanced technologies, B.7.2 [Integrated Circuits, Design Aids – Placement and routing General Terms Algorithms, Design, Experimentation, Performance
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.4109; http://icims.csl.uiuc.edu/~dchen/research/FPCNA.pdf
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Subject Terms: Categories and Subject Descriptors B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, Algorithms implemented in hardware General Terms Algorithms, Measurement, Design, Verification Keywords PET, FPGA, Digital Signal Processing, Pulse Timing, Event Localization
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.152.2891; http://www.ee.washington.edu/faculty/hauck/publications/PET_timing_and_localization.pdf
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Subject Terms: Categories and Subject Descriptors B.6.3 [Logic Design, Design Aids—Optimization, B.7.1 [Integrated Circuits, Types and Design Styles—Gate arrays, J.6 [Computer-Aided Engineering, Computer-aided design (CAD) General Terms Algorithms Keywords FPGA, Technology Mapping, Cut Enumeration, Area Recovery, Lossless Synthesis
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Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.556.3220; http://www.blif.org/~satrajit/pubs/2006_FPGA_Improvements_to_FPGA_Tech_Mapping.pdf
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