Search Results - parallel field programmable gate array implementation~

Parallel field programmable gate array implementation of the sum of absolute differences algorithm used in the stereoscopic system.

Authors: Sejai, Mohamed Mansouri, Anass Dosse, Saad Bennani et al.

Source: Telkomnika. Dec2022, Vol. 20 Issue 6, p1307-1316. 10p.

Subject Terms: *FIELD programmable gate arrays, *STEREO vision (Computer science), *ALGORITHMS, *PARALLEL processing, *IMAGING systems

Field-programmable gate array implementation of efficient deep neural network architecture

Authors: Dileep Kumar Reddy, Pottipati Venkata Ramanaiah, Kota

Subject Terms: Deep neural network, Field-programmable gate array, High-speed, Parallel architecture, Pipeline architecture

Relation: https://zenodo.org/records/11565376; oai:zenodo.org:11565376

Availability: https://doi.org/10.11591/ijece.v14i4.pp3863-3875
https://zenodo.org/records/11565376

High-speed field-programmable gate array implementation for mmWave orthogonal frequency-division multiplexing transmitters: design and evaluation

Authors: Puntsri, Kidsanapong Bunsri, Bussakorn Suthisopapan, Puripong et al.

Contributors: Puntsri, Kidsanapong Bunsri, Bussakorn Suthisopapan, Puripong et al.

Source: International Journal of Electrical and Computer Engineering (IJECE); Vol 15, No 4: August 2025; 3813-3823 ; 2722-2578 ; 2088-8708 ; 10.11591/ijece.v15i4

Subject Terms: Telecommunication, Field-programmable gate array, Inverse fast Fourier transform, Millimeter wave, Orthogonal frequency-division multiplexing, Radix-2 algorithm, Wireless communications

File Description: application/pdf

Relation: https://ijece.iaescore.com/index.php/IJECE/article/view/37804/18347; https://ijece.iaescore.com/index.php/IJECE/article/view/37804

Availability: https://ijece.iaescore.com/index.php/IJECE/article/view/37804
https://doi.org/10.11591/ijece.v15i4.pp3813-3823

An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Gate Array Implementation

Authors: Hao-Yu Wang Zhong-Xun Wang Shuo Shang

Source: Applied Sciences, Vol 14, Iss 12, p 5162 (2024)

Subject Terms: LDPC, NMS, FPGA, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999

File Description: electronic resource

Relation: https://www.mdpi.com/2076-3417/14/12/5162; https://doaj.org/toc/2076-3417

Access URL: https://doaj.org/article/106c7b2fd9cb4343b9c123bf796bece7

A novel parallel algorithm for surface editing and its FPGA implementation

Authors: Liu, Yukun

Subject Terms: 006.6, G450 Multi-media Computing Science, surface modelling, computer graphics, field programmable gate array, FPGA, OpenGL architecture, surface editing

Access URL: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606677

Efficient field-programmable gate array implementation of CCSDS 121.0-B-2 lossless data compression algorithm for image compression

Authors: Kranitis, N. Sideris, I. Tsigkanos, A. Theodorou, G. Paschalis, A. Vitulli, R.

Index Terms: scientific_publication_article, Scientific publication - Journal Article

URL: https://pergamos.lib.uoa.gr/uoa/dl/object/uoadl:3069956

Theory and implementation of a very high throughput true random number generator in field programmable gate array

Contributors: Xu, Chao [Department of Modern Physics, University of Science and Technology of China, Hefei 230026 (China)]

Source: Review of Scientific Instruments; 87; 4; Other Information: (c) 2016 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)

File Description: Medium: X; Size: page(s) 044704-044704.9

Access URL: http://www.osti.gov/scitech/biblio/22597138

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

Contributors: Zin, M. [Malaysian Nuclear Agency (Nuclear Malaysia), Bangi, 43000 KAJANG (Malaysia)]

Source: AIP Conference Proceedings; 1584; 1; Conference: iNuSTEC2013: International nuclear science, technology and engineering conference 2013, Kuala Lumpur (Malaysia), 30 Sep - 2 Oct 2013; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)

File Description: Medium: X; Size: page(s) 69-72

Access URL: http://www.osti.gov/scitech/biblio/22266089

A Convolutional Tsetlin Machine-based Field Programmable Gate Array Accelerator for Image Classification

Authors: Tunheim, Svein Anders Lei, Jiao Shafik, Rishad et al.

Relation: Universitetet i Agder: CAIR

Availability: https://hdl.handle.net/11250/3156292

High-Perfomance Spectral Element Methods on Field-Programmable Gate Arrays: Implementation, Evaluation, and Future Projection

Authors: Karp, Martin Podobas, Artur Jansson, Niclas et al.

Source: Swedish e-Science Research Centre Proceedings of the 35rd IEEE International Parallel & Distributed Processing Symposium, May , 2021 Portland, Oregon, USA.

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-296311

Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm.

Authors: An Hung Nguyen Guillemette, Thomas Lambert, Andrew J. et al.

Source: Journal of Electronic Imaging; Sep/Oct2017, Vol. 26 Issue 5, p1-15, 15p

Subject Terms: IMAGE registration, FIELD programmable gate arrays, KERNEL operating systems, COMPUTATIONAL complexity, OPTICAL flow

Convolutional Neural Network Model Compression Method for Software—Hardware Co-Design.

Authors: Jang, Seojin Liu, Wei Cho, Yongbeom

Source: Information. Oct2022, Vol. 13 Issue 10, p451-N.PAG. 15p.

Subject Terms: *Computer software, *Parallel processing, Convolutional neural networks, Participatory design, Gate array circuits, Graphics processing units, Systems on a chip

Synchronous Optimal Modulation for Medium voltage Multi-phase Machines: Implementation of three-level modulators in Field Programmable Gate Arrays

Authors: Maharjan, Mamta Undeland, Tore Marvin Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elkraftteknikk

Contributors: Maharjan, Mamta Undeland, Tore Marvin Norges teknisk-naturvitenskapelige universitet, Fakultet for informasjonsteknologi, matematikk og elektroteknikk, Institutt for elkraftteknikk

Availability: http://hdl.handle.net/11250/257468

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation.

Authors: Kyrkou, Christos Theocharides, Theocharis

Source: Journal of Electronic Imaging; Jul/Aug2016, Vol. 25 Issue 4, p1-14, 14p

Subject Terms: OBJECT recognition (Computer vision), FIELD programmable gate arrays, EDGE detection (Image processing), COMPUTER vision, CAMERAS, DEPTH gage, HARDWARE design & construction

Parallel fpga routing based on the operator formulation

Authors: Moctar, Yehdhih Ouid Mohammed Brisk, Philip

Subject Terms: Built Environment and Design, Architecture, Engineering, Electrical Engineering, Field Programmable Gate Array, Routing, Routing Resource Graph, Maze Expansion, Irregular Algorithm, Software Transactional Memory

Access URL: https://escholarship.org/uc/item/0jp9j4dj

Field programmable gate array implementation of variable‐bins high efficiency video coding CABAC decoder with path delay optimisation.

Authors: Menasri, Wahiba Skoudarli, Abdellah Belhadj, Aichouche et al.

Source: IET Image Processing (Wiley-Blackwell); May2019, Vol. 13 Issue 6, p954-963, 10p

Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays

Authors: De la Cruz, Juan Alberto

Source: All Graduate Theses and Dissertations, Spring 1920 to Summer 2023

Subject Terms: Accelerator, FPGA, Image Processing, Integral Image, Systolic Arrays, Computer Engineering

File Description: application/pdf

Relation: https://digitalcommons.usu.edu/etd/854; https://digitalcommons.usu.edu/context/etd/article/1850/viewcontent/JuanAlbertoDelaCruz_thesis.pdf

Availability: https://digitalcommons.usu.edu/etd/854
https://doi.org/10.26076/22d9-3726
https://digitalcommons.usu.edu/context/etd/article/1850/viewcontent/JuanAlbertoDelaCruz_thesis.pdf

Field programmable gate array implementation of an adaptive filtering based noise reduction and enhanced compression technique for healthcare applications

Authors: Aruna, Viswanadham Baby Koti Lakshmi Ekambaram, Chitra Padmaja, Mididoddi

Source: Transactions on Emerging Telecommunications Technologies ; volume 34, issue 1 ; ISSN 2161-3915 2161-3915

Availability: http://dx.doi.org/10.1002/ett.4654
https://onlinelibrary.wiley.com/doi/pdf/10.1002/ett.4654
https://onlinelibrary.wiley.com/doi/full-xml/10.1002/ett.4654

Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays

Authors: Juan A. De La Cruz Prof Paul Israelsen The Pennsylvania State University CiteSeerX Archives

Contributors: Juan A. De La Cruz Prof Paul Israelsen The Pennsylvania State University CiteSeerX Archives

Source: http://www.ece.usu.edu/grad/reports_theses_disseratations/2011/Juan_De_La_Cruz/thesis.pdf.

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.190.7115; http://www.ece.usu.edu/grad/reports_theses_disseratations/2011/Juan_De_La_Cruz/thesis.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.190.7115
http://www.ece.usu.edu/grad/reports_theses_disseratations/2011/Juan_De_La_Cruz/thesis.pdf

2D Parallel Architecture for Morphological Operators Supporting Multiple Shaped Structuring Elements.

Authors: ELLOUMI, Hajer KRID, Mohamed SELLAMI, Dorra

Source: Procedia Computer Science. 2018, Vol. 126, p695-702. 8p.

Subject Terms: Parallel processing, Field programmable gate arrays, Electronic data processing, Computer input-output equipment, High resolution imaging