Search Results - parallel field programmable gate array implementation*

Parallel multi‐rate simulation scheme for modular multilevel converter‐based high‐voltage direct current with accurate simulation of high‐frequency characteristics and field programmable gate array‐based implementation

Authors: Chongru Liu Yanqi Hou Haoyun Dong et al.

Source: High Voltage, Vol 10, Iss 1, Pp 17-31 (2025)

Subject Terms: Electrical engineering. Electronics. Nuclear engineering, TK1-9971, Electricity, QC501-721

File Description: electronic resource

Relation: https://doaj.org/toc/2397-7264

Access URL: https://doaj.org/article/7e8015e7250a428ebfe4d93cbe6f02ad

Field Programmable Gate Array (FPGA) Implementation of Parallel Jacobi for Eigen-Decomposition in Direction of Arrival (DOA) Estimation Algorithm

Authors: Shuang Zhou Li Zhou

Source: Remote Sensing, Vol 16, Iss 20, p 3892 (2024)

Subject Terms: eigen-decomposition, parallel Jacobi, FPGA, CORDIC, Science

File Description: electronic resource

Relation: https://www.mdpi.com/2072-4292/16/20/3892; https://doaj.org/toc/2072-4292

Access URL: https://doaj.org/article/21fb8e83e2e3426eaeb5519ed42e49b3

Parallel field programmable gate array implementation of the sum of absolute differences algorithm used in the stereoscopic system.

Authors: Sejai, Mohamed Mansouri, Anass Dosse, Saad Bennani et al.

Source: Telkomnika. Dec2022, Vol. 20 Issue 6, p1307-1316. 10p.

Subject Terms: *FIELD programmable gate arrays, *STEREO vision (Computer science), *ALGORITHMS, *PARALLEL processing, *IMAGING systems

Performance evaluation of the inverse real-valued fast Fourier transform on field programmable gate array platforms using open computing language

Authors: Li Liu Sida Yang Haoyu Tan et al.

Source: PeerJ Computer Science, Vol 11, p e3313 (2025)

Subject Terms: Real-valued FFT, OpenCL, FPGA, High-level synthesis, Pipeline, Parallel computing, Electronic computers. Computer science, QA75.5-76.95

File Description: electronic resource

Relation: https://peerj.com/articles/cs-3313.pdf; https://peerj.com/articles/cs-3313/; https://doaj.org/toc/2376-5992

Access URL: https://doaj.org/article/f417b92a4def4cae86963e7cb28396c1

The Implementation of the Physical Unclonable Function in a Field-Programmable Gate Array for Enhancing Hardware Security

Authors: Kuang-Hao Lin Wei-Hao Wang I-Chen Wang

Source: Engineering Proceedings, Vol 92, Iss 1, p 23 (2025)

Subject Terms: PUF, chip security, FPGA, hardware, Engineering machinery, tools, and implements, TA213-215

File Description: electronic resource

Relation: https://www.mdpi.com/2673-4591/92/1/23; https://doaj.org/toc/2673-4591

Access URL: https://doaj.org/article/a0b325a53b8d4b018342e3863aa1cb8b

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Authors: Ionel Zagan Vasile Gheorghiţă Găitan

Source: PeerJ Computer Science, Vol 9, p e1300 (2023)

Subject Terms: Field-programmable gate arrays (FPGAs), MIPS32, MicroBlaze, ARM, Asynchronous event handling, Electronic computers. Computer science, QA75.5-76.95

File Description: electronic resource

Relation: https://peerj.com/articles/cs-1300.pdf; https://peerj.com/articles/cs-1300/; https://doaj.org/toc/2376-5992

Access URL: https://doaj.org/article/58bcf22ecbfa41c3bb44fc4e59eaf321

High‐speed and reduced energy delay product TCAM on FPGA for network routers.

Authors: Sankara Vadivel, Sridhar Raj Ramapackiam, Shantha Selvakumari

Source: ETRI Journal. Jun2025, Vol. 47 Issue 3, p505-517. 13p.

Subject Terms: Network routers, Field programmable gate arrays, Parallel processing, Resource allocation

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution

Authors: Lianye Liao Xinyi Wu Ye Chen et al.

Source: Scientific Reports, Vol 15, Iss 1, Pp 1-12 (2025)

Subject Terms: Field programmable gate array (FPGA), Information reconciliation (IR), Polar codes, Discrete variable quantum key distribution (DV-QKD), Medicine, Science

File Description: electronic resource

Relation: https://doaj.org/toc/2045-2322

Access URL: https://doaj.org/article/8ba9f13367e541dca06f202a89335c95

An Improved Low-Density Parity-Check Decoder and Its Field-Programmable Gate Array Implementation

Authors: Hao-Yu Wang Zhong-Xun Wang Shuo Shang

Source: Applied Sciences, Vol 14, Iss 12, p 5162 (2024)

Subject Terms: LDPC, NMS, FPGA, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999

File Description: electronic resource

Relation: https://www.mdpi.com/2076-3417/14/12/5162; https://doaj.org/toc/2076-3417

Access URL: https://doaj.org/article/106c7b2fd9cb4343b9c123bf796bece7

Performance Estimation of Low Power and Area-Efficient Parallel Pipelined FFT

Authors: Surya P Arunachalaperumal C Dhilipkumar S

Source: Measurement Science Review, Vol 25, Iss 3, Pp 134-140 (2025)

Subject Terms: low power fast fourier transform, vedic multiplier, bit inversion technique, look-up table, field programmable gate array, 5g application, Mathematics, QA1-939

File Description: electronic resource

Relation: https://doaj.org/toc/1335-8871

Access URL: https://doaj.org/article/e2cce4e2f9544eae910a1118c33071f5

Design and implementation of reconfigurable ASK and FSK modulation and demodulation algorithm on FPGA (Field Programmable Gate Array)

Authors: Md Wahid Sadiq Md Ahasan Kabir

Source: Sensors International, Vol 3, Iss , Pp 100155- (2022)

Subject Terms: FPGA, Modulation, ASK, FSK, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

File Description: electronic resource

Relation: http://www.sciencedirect.com/science/article/pii/S2666351121000760; https://doaj.org/toc/2666-3511

Access URL: https://doaj.org/article/926924c62df84789b22f0879a0e1f2db

FIELD-PROGRAMMABLE GATE ARRAY (FPGA) MODULAR IMPLEMENTATION

Towards Fast Implementation of Complex RNS Components on FPGAs

Authors: Sabbagh Molahosseini Amir Alsadat Emrani Azadeh

Source: Наука. Инновации. Технологии, Vol 0, Iss 4, Pp 86-95 (2022)

Subject Terms: residue number system (rns), field programmable gate array fpga), parallel prefix adders, система остаточных классов (rns), программируе-мая вентильная матрица (fpga), параллельный сумматор, Geography (General), G1-922

File Description: electronic resource

Relation: https://scienceit.elpub.ru/jour/article/view/429; https://doaj.org/toc/2308-4758

Access URL: https://doaj.org/article/677593be3c9e46158e118bca88c6182a

A novel parallel algorithm for surface editing and its FPGA implementation

Authors: Liu, Yukun

Subject Terms: 006.6, G450 Multi-media Computing Science, surface modelling, computer graphics, field programmable gate array, FPGA, OpenGL architecture, surface editing

Access URL: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606677

Parallel Implementation of GPU-Based LDPC Enhanced Quasi-Maximum Likelihood Decoder

Authors: KONG Feiyue, JIANG Xueqin, WAN Xuefen, CHEN Sijing, CUI Jian, YANG Yi

Source: Jisuanji gongcheng, Vol 46, Iss 5, Pp 207-215 (2020)

Subject Terms: low density parity check(ldpc) code, gpu parallel decoding, enhanced quasi-maximum likelihood(eqml) decoder, belief propagation(bp) decoder, field programmable gate array(fpga), Computer engineering. Computer hardware, TK7885-7895, Computer software, QA76.75-76.765

File Description: electronic resource

Relation: https://www.ecice06.com/fileup/1000-3428/PDF/20200529.pdf; https://doaj.org/toc/1000-3428

Access URL: https://doaj.org/article/109310ff06dd4b20bd20a650c0c48022

DISORDERED PARALLEL MAXIMUM FLOW/MINIMUM CUT METHOD IMPLEMENTED BY ENERGY-EFFICIENT FIELD-PROGRAMMABLE GATE ARRAY (FPGA)

Reliable Design and Control Implementation of Parallel DC/DC Converter for High Power Charging System

Authors: Qing Zhou Yuelei Xu Jarhinbek Rasol et al.

Source: Machines, Vol 10, Iss 12, p 1162 (2022)

Subject Terms: reliability, N + 1 system, fault-tolerant, thermal sharing, field programmable gate array, Mechanical engineering and machinery, TJ1-1570

File Description: electronic resource

Relation: https://www.mdpi.com/2075-1702/10/12/1162; https://doaj.org/toc/2075-1702

Access URL: https://doaj.org/article/3690b1a9e32b4affbdf8a39c94cb00d9

Parallel Optimisation and Implementation of a Real-Time Back Projection (BP) Algorithm for SAR Based on FPGA

Authors: Yue Cao Shuchen Guo Shuai Jiang et al.

Source: Sensors, Vol 22, Iss 6, p 2292 (2022)

Subject Terms: synthetic aperture radar (SAR), back-projection algorithm (BP), real-time image processing, field-programmable gate array (FPGA), Chemical technology, TP1-1185

File Description: electronic resource

Relation: https://www.mdpi.com/1424-8220/22/6/2292; https://doaj.org/toc/1424-8220

Access URL: https://doaj.org/article/5fcdd80b614946b5a15de9dbb9098867

Parallel field programmable gate array particle filtering architecture for real-time neural signal processing

Authors: Iyad Obeid John Mountney Dennis Silage

Source: 2010 Annual International Conference of the IEEE Engineering in Medicine and Biology. :2674-2677

Subject Terms: Neurons, Likelihood Functions, Time Factors, Computers, Models, Neurological, Brain, Bayes Theorem, Signal Processing, Computer-Assisted, Equipment Design, 03 medical and health sciences, 0302 clinical medicine, Humans, Computer Simulation, Algorithms, Software

Access URL: https://pubmed.ncbi.nlm.nih.gov/21096196
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005626626
https://ieeexplore.ieee.org/document/5626626/
http://ieeexplore.ieee.org/document/5626626/
https://www.ncbi.nlm.nih.gov/pubmed/21096196

Hardware-accelerated real-time FIR filtering for audio applications using FPGAs

Authors: Chenmu Ji Weibei Fan

Source: Intelligent and Converged Networks, Vol 6, Iss 3, Pp 209-222 (2025)

Subject Terms: field-programmable gate array (fpga), real-time audio processing, wm8731 codec, finite impulse response (fir) filter, Telecommunication, TK5101-6720

File Description: electronic resource

Relation: https://www.sciopen.com/article/10.23919/ICN.2025.0017; https://doaj.org/toc/2708-6240

Access URL: https://doaj.org/article/2152b1f541854f72a1e1d1f93d98a573