Suchergebnisse - hardware (implementation OR implementation) of nonnumerical algorithms (vlsi algorithms, etc.)~

A new algorithm for the elimination of common subexpressions in hardware implementation of digital filters by using genetic programming

Autoren: W.C. Miller Majid Ahmadi H. Safiri et al.

Quelle: Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. :319-328

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), digital filter, ASIC, Learning and adaptive systems in artificial intelligence, genetic algorithm, 0211 other engineering and technologies, 0202 electrical engineering, electronic engineering, information engineering, common subexpressions, 02 engineering and technology, integer multiplication

Dateibeschreibung: application/xml

Zugangs-URL: https://link.springer.com/article/10.1023/A:1015385120447
https://doi.org/10.1023/A:1015385120447
https://dblp.uni-trier.de/db/conf/asap/asap2000.html#SafiriAJM00
https://rd.springer.com/content/pdf/10.1023%2FA%3A1015385120447.pdf
https://ieeexplore.ieee.org/document/862402

Modular switched-resistor ANN chip for character recognition using novel parallel VLSI architecture

Autoren: Rehan, Sameh E. Elmasry, Mohamed I.

Schlagwörter: multi- layer perceptron, back-propagation learning algorithm, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Pattern recognition, speech recognition, character recognition, Learning and adaptive systems in artificial intelligence, VLSI implementation, hardware implementation, VLSI circuits, Circuits, networks, switched-resistor circuits, artificial neural networks, sampled-data circuits

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/529794

zbMATH Open Web Interface contents unavailable due to conflicting licenses.

Autoren: zbMATH Open Web Interface contents unavailable due to conflicting licenses.

Schlagwörter: Computer system organization, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Learning and adaptive systems in artificial intelligence

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1127805

zbMATH Open Web Interface contents unavailable due to conflicting licenses.

Autoren: zbMATH Open Web Interface contents unavailable due to conflicting licenses.

Schlagwörter: Finite difference methods for boundary value problems involving PDEs, Iterative numerical methods for linear systems, Computational methods for sparse matrices, Laplace operator, Helmholtz equation (reduced wave equation), Poisson equation, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1428276

Beyond-Binary Arithmetic: Algorithms and VLSI Implementations: Beyond-binary arithmetic: Algorithms and VLSI implementations

Autoren: Tatsuo Higuchi Takafumi Aoki

Quelle: Interdisciplinary Information Sciences. 6:75-98

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Mathematical problems of computer architecture, computer arithmetic algorithms

Dateibeschreibung: application/xml

Zugangs-URL: https://www.jstage.jst.go.jp/article/iis/6/1/6_1_75/_pdf
https://zbmath.org/1491723
https://doi.org/10.4036/iis.2000.75
http://ci.nii.ac.jp/naid/110000071715

A vector quantization algorithm suitable for VLSI implementation

Autoren: Min Hao Zhou Ting Zhang Qian-Ling et al.

Quelle: 2nd International Conference on ASIC. :23-26

Schlagwörter: 0508 media and communications, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 05 social sciences, VLSI implementation, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Image processing (compression, reconstruction, etc.) in information and communication theory

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1553672
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?isnumber=12233&arnumber=562741&count=115&index=7
http://ieeexplore.ieee.org/iel3/4267/12233/00562741.pdf

The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations: The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations.

Autoren: Heinrich Meyr H. Dawid

Quelle: IEEE Transactions on Computers. 45:307-318

Schlagwörter: VLSI architecture, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), reduncant number systems, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Nonnumerical algorithms, Mathematical problems of computer architecture

Dateibeschreibung: application/xml

Zugangs-URL: https://core.ac.uk/display/36592121
https://ieeexplore.ieee.org/document/485569/
https://dblp.uni-trier.de/db/journals/tc/tc45.html#DawidM96
http://ieeexplore.ieee.org/document/485569/
https://doi.org/10.1109%2f12.485569
https://www.computer.org/csdl/journal/tc/1996/03/t0307/13rRUxD9h4i

Efficient processor arrays for the implementationof the generalised predictive-control algorithm: Efficient processor arrays for the implementation of the generalised predictive-control algorithm

Autoren: T. Chronopoulos N. Koussoulas Anthony Tzes et al.

Quelle: IEE Proceedings - Control Theory and Applications. 145:47-54

Schlagwörter: generalized predictive control algorithm, 0209 industrial biotechnology, Design techniques (robust design, computer-aided design, etc.), Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, parallel algorithms, processor array architectures, 02 engineering and technology, Control/observation systems involving computers (process control, etc.)

Dateibeschreibung: application/xml

Zugangs-URL: https://digital-library.theiet.org/content/journals/10.1049/ip-cta_19981637
https://nyuscholars.nyu.edu/en/publications/efficient-processor-arrays-for-the-implementation-of-the-generali

An Efficient Algorithm and Parallel Implementations for Binary and Residue Number Systems: An efficient algorithm and parallel implementations for binary and residue number systems

Autoren: C.N. Zhang D.Y.Y. Yun B. Shirazi

Quelle: Journal of Symbolic Computation. 15:451-462

Schlagwörter: parallelism, Algebra and Number Theory, digital signal processing, 02 engineering and technology, symbolic computation, Computational Mathematics, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Switching theory, application of Boolean algebra, Boolean functions, Computational number theory, 0202 electrical engineering, electronic engineering, information engineering, Distributed algorithms, residue number system, Congruences, primitive roots, residue systems, VLSI hardware design

Dateibeschreibung: application/xml

Zugangs-URL: https://dialnet.unirioja.es/servlet/articulo?codigo=345217
https://core.ac.uk/display/82573125
https://www.sciencedirect.com/science/article/pii/S0747717183710308
https://www.sciencedirect.com/science/article/abs/pii/S0747717183710308
https://dblp.uni-trier.de/db/journals/jsc/jsc15.html#ZhangSY93

A proof of the nonrestoring division algorithm and its implementation on an ALU

Autoren: Diederik Verkest Luc Claesen H. De Man

Quelle: Formal Methods in System Design. 4:5-31

Schlagwörter: correctness, Boyer- Moore theorem-proving system, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), ALU implementation, Switching theory, application of Boolean algebra, Boolean functions, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Theorem proving (deduction, resolution, etc.), nonrestoring division algorithm

Dateibeschreibung: application/xml

VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers: VLSI implementation of the multistage detector for next generation wideband CDMA receivers

Autoren: Xu, Gang Rajagopal, Sridhar Cavallaro, Joseph R. et al.

Weitere Verfasser: Xu, Gang Rajagopal, Sridhar Cavallaro, Joseph R. et al.

Quelle: Information Technology: Transmission, Processing and Storage ISBN: 0792376919

Schlagwörter: Computing methodologies and applications, Network design and communication in computer systems, real-time implementation, 05 social sciences, 02 engineering and technology, CDMA, multistage detection algorithm, 0508 media and communications, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), widemand code division multiple access, multiuser detection, inteference cancellation, multistage detector, 0202 electrical engineering, electronic engineering, information engineering

Dateibeschreibung: application/xml; application/pdf

Zugangs-URL: https://scholarship.rice.edu/bitstream/1911/20227/1/Raj2001May1VLSIimplem.PDF
https://zbmath.org/1747880
https://doi.org/10.1023/a:1014086523082

Systolic array implementation of some iterative algorithms for solving systems of linear algebraic equations

Autoren: Yu. S. Kanevskii L. D. Elfimova R. Vyzhikovski

Quelle: Cybernetics and Systems Analysis. 28:775-784

Schlagwörter: systolic array, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), iterative algorithms, Graph theory (including graph drawing) in computer science, linear algebra algorithms, 0211 other engineering and technologies, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Direct numerical methods for linear systems and matrix inversion, lattice graphs

Dateibeschreibung: application/xml

Zugangs-URL: https://link.springer.com/article/10.1007/BF01131857

A Framework for High Level Estimations of Signal Processing VLSI Implementations: A framework for high level estimations of signal processing VLSI implementations

Autoren: Diguet, Jean-Philippe Sentieys, Olivier Chillet, Daniel et al.

Weitere Verfasser: Diguet, Jean-Philippe Sentieys, Olivier Chillet, Daniel et al.

Quelle: Journal of VLSI signal processing systems for signal, image and video technology. 25:261-284

Schlagwörter: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], High Level Synthesis, Transformations, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), digital signal processing, VLSI circuits, Estimation, LMS, VLSI

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1523684
https://doi.org/10.1023/a:1008191708726
https://hal.science/hal-00089488v1
https://doi.org/10.1023/a:1008191708726

A One-Dimensional Analog VLSI Implementation for Nonlinear Real-Time Signal Preprocessing: A one-dimensional analog VLSI implementation for nonlinear real-time signal preprocessing

Autoren: Rolf-Rainer Grigat Christoph Schnörr K. Wiehler et al.

Quelle: Real-Time Imaging. 7:127-142

Schlagwörter: Computing methodologies and applications, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Computing methodologies for image processing, Machine vision and scene understanding

Dateibeschreibung: application/xml

Basic hardware module for a nonlinear programming algorithm and applications

Autoren: Shin-Yeu Lin

Quelle: Automatica. 33:1579-1586

Schlagwörter: 0209 industrial biotechnology, 02 engineering and technology, nonlinear system, Control/observation systems involving computers (process control, etc.), VLSI-array processor architecture, optimal control, 0203 mechanical engineering, Nonlinear programming, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), discrete-time optimization, nonlinear programming, Nonlinear systems in control theory, control constraints, hardware module

Dateibeschreibung: application/xml

Zugangs-URL: https://www.sciencedirect.com/science/article/pii/S0005109897000538
https://ir.nctu.edu.tw:443/handle/11536/422
https://dblp.uni-trier.de/db/journals/automatica/automatica33.html#Lin97a
https://ir.nctu.edu.tw/bitstream/11536/422/1/A1997XU55600015.pdf

A high-speed residue-to-binary converter for three-moduli (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) RNS and a scheme for its VLSI implementation: A high-speed residue-to-binary converter for three-moduli \((2^k, 2^k -1, 2^{k-1} -1)\) RNS and a scheme for its VLSI implementation

Autoren: Wang, Wei Swamy, M. N. S. Ahmad, M. O. et al.

Quelle: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 47:1576-1581

Schlagwörter: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), digital signal processing, VLSLI implementation, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Mathematical problems of computer architecture

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1632335
https://doi.org/10.1109/82.899659

VLSI architecture of modified Euclidean algorithm for Reed–Solomon code: VLSI architecture of modified Euclidean algorithm for Reed-Solomon code.

Autoren: Yaotsu Chang J.H. Jeng Trieu-Kien Truong

Quelle: Information Sciences. 155:139-150

Schlagwörter: VLSI architecture, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), Decoding, Reed-Solomon code, 0202 electrical engineering, electronic engineering, information engineering, Error correcting code, Multiplicative structure, Euclidean algorithm, greatest common divisors, 02 engineering and technology, decoding algorithm, Reliability, testing and fault tolerance of networks and computer systems, Berlekamp's key equation

Dateibeschreibung: application/xml

Zugangs-URL: http://ecite.utas.edu.au/29917
https://www.sciencedirect.com/science/article/pii/S0020025503001543
http://ir.lib.isu.edu.tw/handle/987654321/9444
https://dblp.uni-trier.de/db/journals/isci/isci155.html#ChangTJ03

An Efficient In-Place VLSI Architecture for Viterbi Algorithm: An efficient in-place VLSI architecture for Viterbi algorithm

Autoren: Yun-Nan Chang

Quelle: Journal of VLSI signal processing systems for signal, image and video technology. 33:317-324

Schlagwörter: trace-back, 0508 media and communications, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 05 social sciences, ACS unit, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Viterbi decoder, register-exchange

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/1970997
https://doi.org/10.1023/a:1022246815354
https://rd.springer.com/article/10.1023/A%3A1022246815354
https://link.springer.com/10.1023/A:1022246815354
https://link.springer.com/article/10.1023%2FA%3A1022246815354
https://dblp.uni-trier.de/db/journals/vlsisp/vlsisp33.html#Chang03

VLSI implementations of number theoretic techniques in signal processing

Autoren: Graham A. Jullien W.C. Miller Neil M. Wigley

Quelle: Integration. 16:293-313

Schlagwörter: polynomial rings, real-time digital signal processing, bit-level systolic arrays, Miscellaneous applications of number theory, 02 engineering and technology, VLSI signal processors, dynamic logic, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), arithmetic circuits, inner product computations, 0202 electrical engineering, electronic engineering, information engineering, residue number systems, pipelined computation, Circuits, networks

Dateibeschreibung: application/xml

Zugangs-URL: https://zbmath.org/567696
https://doi.org/10.1016/0167-9260(93)90026-9
https://www.sciencedirect.com/science/article/abs/pii/0167926093900269
https://dblp.uni-trier.de/db/journals/integration/integration16.html#JullienWM93
http://www.sciencedirect.com/science/article/pii/0167926093900269

VLSI algorithms and architectures for complex householder transformation with applications to array processing: VLSI algorithms and architectures for complex Householder transformation with applications to array processing

Autoren: K.J.R. Liu Kung Yao S.F. Hsieh et al.

Quelle: Journal of VLSI signal processing systems for signal, image and video technology. 4:53-68

Schlagwörter: Numerical algorithms for specific classes of architectures, Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Dateibeschreibung: application/xml

Zugangs-URL: https://drum.lib.umd.edu/bitstream/1903/5131/1/TR_91-84.pdf
https://zbmath.org/644410
https://doi.org/10.1007/bf00930618
https://dblp.uni-trier.de/db/journals/vlsisp/vlsisp4.html#TangLHY92
https://doi.org/10.1007/BF00930618
https://link.springer.com/article/10.1007/BF00930618
https://drum.lib.umd.edu/handle/1903/5131
https://rd.springer.com/article/10.1007/BF00930618
https://drum.lib.umd.edu/bitstream/1903/5131/1/TR_91-84.pdf