Search Results - field-programmable gate array (fpga) implementations

Comparative Analysis of Bandpass IIR Filters on Microphone PDM Signal for FPGA Implementation.

Authors: Vulic, Lukrecia Aleksi, Ivan Matić, Tomislav

Source: Central European Conference on Information & Intelligent Systems; 2025, p53-60, 8p

Subject Terms: BUTTERWORTH filters (Signal processing), FIELD programmable gate arrays, ELECTRONIC data processing, QUANTIZATION (Physics), BANDPASS filters, MEAN square algorithms

Implementation of digital processing algorithms for real time radiation spectroscopy applications

Implementação de algoritmos de processamento digital em tempo real para aplicações de espectroscopia de radiação

Authors: Madeira, Gil Ramos

Subject Terms: Multi channel Analyser, Field Programmable Gate Array (FPGA), Spectroscopy, VHDL, Analisador Multi canal, Arranjo de portas programáveis em campo (FPGA), Espetroscopia

Availability: https://hdl.handle.net/10316/117808

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Authors: Berg, M Kim, H Phan, A et al.

Subject Terms: Electronics And Electrical Engineering

Access URL: https://ntrs.nasa.gov/citations/20150018112

Vulnerability Analysis of Trivium FPGA Implementations

Authors: F. E. Potestad-Ordonez C. J. Jimenez-Fernandez M. Valencia-Barrero et al.

Contributors: F. E. Potestad-Ordonez C. J. Jimenez-Fernandez M. Valencia-Barrero et al.

Source: Digital.CSIC. Repositorio Institucional del CSIC
Consejo Superior de Investigaciones Científicas (CSIC)
instname
idUS. Depósito de Investigación de la Universidad de Sevilla
Universidad de Sevilla (US)

Subject Terms: Fault attack, field-programmable gate array (FPGA) implementation, Vulnerability analysis, Trivium, 02 engineering and technology, Stream ciphers, 01 natural sciences, 7. Clean energy, stream cipher, vulnerability analysis, 0104 chemical sciences, Stream Cipher, 13. Climate action, Implementation, 0202 electrical engineering, electronic engineering, information engineering, Field programmable gate array (FPGA), Fault Attack

File Description: application/pdf

Access URL: http://hdl.handle.net/10261/195257
https://hdl.handle.net/11441/105833
https://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#Potestad-Ordonez17
https://digital.csic.es/handle/10261/195257
https://ieeexplore.ieee.org/document/8052547
https://doi.org/10.1109/TVLSI.2017.2751151
https://idus.us.es/handle//11441/105833

JPEG decoder implementation on FPGA using dynamic partial reconfiguration

Authors: Rodrigues, Tiago Augusto Nunes Véstias, Mário Pereira RCIPL

Contributors: Rodrigues, Tiago Augusto Nunes Véstias, Mário Pereira RCIPL

Source: urn:tid:201223546

Subject Terms: Dynamic reconfiguration, Reconfigurable computing, JPEG image decoding, Field-programmable gate array, Reconfiguração dinâmica, Sistemas computacionais reconfiguráveis, Decodificação de imagens JPEG

File Description: application/pdf

Availability: http://hdl.handle.net/10400.21/5375

Vulnerability Analysis of Trivium FPGA Implementations

Authors: Potestad Ordóñez, Francisco Eugenio Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel et al.

Contributors: Potestad Ordóñez, Francisco Eugenio Jiménez Fernández, Carlos Jesús Valencia Barrero, Manuel et al.

Subject Terms: Fault Attack, Field programmable gate array (FPGA), Implementation, Stream Cipher, Trivium, Vulnerability analysis

Relation: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (12), 3380-3389.; TEC2013-45523-R; TEC2016-80549-R; CSIC 201550E039; https://ieeexplore.ieee.org/document/8052547; https://idus.us.es/handle//11441/105833

Availability: https://idus.us.es/handle//11441/105833

Density Encoding Enables Resource-Efficient Randomly Connected Neural Networks

Authors: Kleyko, Denis Kheffache, Mansour Frady, E Paxon et al.

Source: IEEE Transactions on Neural Networks and Learning Systems. 32(8):3777-3783

Subject Terms: Density-based encoding, hyperdimensional computing, random vector functional link (RVFL) networks, Encoding (symbols), Field programmable gate arrays (FPGA), Learning algorithms, Machine learning, Network coding, Stochastic systems, Classification tasks, Computationally efficient, Field-programmable gate array implementations, Functional links, Hidden neurons, Resource-efficient, Stochastic computing, UCI machine learning repository, Neural networks

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:ri:diva-55946

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Authors: McKeown, S. Woods, R.

Source: McKeown, S & Woods, R 2011, ' Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality ' IET COMPUTERS AND DIGITAL TECHNIQUES, vol 5, no. 2, 2, pp. 136-144 . DOI: 10.1049/iet-cdt.2010.0052

Subject Terms: name=Software, Hardware and Architecture, name=Hardware and Architecture, 0202 electrical engineering, electronic engineering, information engineering, name=Electrical and Electronic Engineering, 02 engineering and technology, Electrical and Electronic Engineering, 7. Clean energy, Software

File Description: application/pdf

Access URL: https://pure.qub.ac.uk/ws/files/796069/IET_05728972.pdf
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005728972
https://pure.qub.ac.uk/portal/en/publications/low-power-field-programmable-gate-array-implementation-of-fast-digital-signal-processing-algorithms-characterisation-and-manipulation-of-data-locality(2baa1a6b-4809-47b4-af1d-b233174d1253)/export.html
https://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt5.html#McKeownW11
https://core.ac.uk/display/10065920
https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2010.0052
https://pure.qub.ac.uk/portal/files/796069/IET_05728972.pdf
https://pure.qub.ac.uk/portal/en/publications/low-power-field-programmable-gate-array-implementation-of-fast-digital-signal-processing-algorithms-characterisation-and-manipulation-of-data-locality(2baa1a6b-4809-47b4-af1d-b233174d1253).html

FPGA Implementation(s) of a Scalable Encryption Algorithm

Authors: Macé, François Standaert, François-Xavier Quisquater, Jean-Jacques et al.

Contributors: Macé, François Standaert, François-Xavier Quisquater, Jean-Jacques et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, no. 2, p. 212-216 (2008)

Subject Terms: constrained applications, block ciphers, modular design, 0202 electrical engineering, electronic engineering, information engineering, field-programmable gate array (FPGA) implementations, 02 engineering and technology

Access URL: http://perso.uclouvain.be/fstandae/PUBLIS/52.pdf
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004444553
https://dl.acm.org/doi/10.1109/TVLSI.2007.904139
https://dial.uclouvain.be/pr/boreal/object/boreal:36859
http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4432656&arnumber=4444553&count=17&index=14
https://www.infona.pl/resource/bwmeta1.element.ieee-art-000004444553
https://ieeexplore.ieee.org/document/4444553/
https://hdl.handle.net/2078.1/36859

FPGA Integrated Optofluidic Biosensor for Real-Time Single Biomarker Analysis.

Authors: Sampad, Mohammad Amin, Md Hawkins, Aaron et al.

Source: IEEE Photonics Journal. 14(1)

Subject Terms: Optofluidics, anti-resonant reflecting optical waveguide (ARROW), biophotonics, field programmable gate array (FPGA), real-time, single molecule detection

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/3zd362m2
https://escholarship.org/content/qt3zd362m2/qt3zd362m2.pdf

Customizable FPGA-based hardware accelerator for standard convolution processes applicable to LiDAR data

Acelerador por hardware em FPGA para processos de convolução padrão customizáveis e aplicáveis a dados LiDAR

Authors: Silva, João Pedro Duarte da Fernandes, Duarte Manuel Azevedo Machado, Rui Pedro Oliveira et al.

Contributors: Silva, João Pedro Duarte da Fernandes, Duarte Manuel Azevedo Machado, Rui Pedro Oliveira et al.

Source: urn:tid:202951766

Subject Terms: Convolutional neural network (CNN), Hardware accelerator, Field programmable gate array (FPGA), Light detection and ranging (LiDAR), Quantization, Object detection, Redes neurais convolucionais, Acelerador por hardware, FPGA, LiDAR, Quantização, Deteção de objetos

File Description: application/pdf

Availability: https://hdl.handle.net/1822/77534

Low Latency Demodulation for High-Frequency Atomic Force Microscopy Probes

Authors: Lagrange, Denis Mauran, Nicolas Schwab, Lucien et al.

Contributors: Lagrange, Denis Mauran, Nicolas Schwab, Lucien et al.

Source: IEEE Transactions on Control Systems Technology. 29:2264-2270

Subject Terms: 0301 basic medicine, 0303 health sciences, atomic force microscopy, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, field-programmable gate array (FPGA) implementations, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics, low latency, 03 medical and health sciences, amplitude and phase demodulation, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, [SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

File Description: application/pdf

Access URL: https://hal.laas.fr/hal-02974151/file/FINAL%20VERSION.pdf
https://dblp.uni-trier.de/db/journals/tcst/tcst29.html#LagrangeMSL21
https://ieeexplore.ieee.org/document/9229238
http://ieeexplore.ieee.org/document/9229238

Rapid geodesic mapping of brain functional connectivity: implementation of a dedicated co-processor in a field-programmable gate array (FPGA) and application to resting state functional MRI.

Authors: Minati L Cercignani M Chan D

Source: Medical engineering & physics [Med Eng Phys] 2013 Oct; Vol. 35 (10), pp. 1532-9. Date of Electronic Publication: 2013 Jun 05.

Publication Type: Journal Article

Journal Info: Publisher: Butterworth-Heinemann Country of Publication: England NLM ID: 9422753 Publication Model: Print-Electronic Cited Medium: Internet ISSN: 1873-4030 (Electronic) Linking ISSN: 13504533 NLM ISO Abbreviation: Med Eng Phys Subsets: MEDLINE

MeSH Terms: Computers* , Magnetic Resonance Imaging* , Software*, Brain/*physiology , Brain Mapping/*instrumentation , Nerve Net/*physiology , Rest/*physiology, Adult ; Female ; Humans ; Time Factors

Implementation Strategy of Convolution Neural Networks on Field Programmable Gate Arrays for Appliance Classification Using the Voltage and Current (V-I) Trajectory

Authors: Baptista, Darío Mostafa, Sheikh Shanawaz Pereira, Lucas et al.

Contributors: Baptista, Darío Mostafa, Sheikh Shanawaz Pereira, Lucas et al.

Subject Terms: Non-intrusive load monitoring, Convolution neural network, V-I trajectory, Hardware classifier, FPGA, Faculdade de Ciências Exatas e da Engenharia

File Description: application/pdf

Availability: http://hdl.handle.net/10400.13/5644

FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field

Authors: Li, Hao Huang, Jian Sweany, Philip et al.

Source: Journal of Systems Architecture. 54:1077-1088

Subject Terms: Elliptic curve cryptography, Tate pairing, Field programmable gate array, Parallel processing, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 16. Peace & justice, Galois field arithmetic

Access URL: https://digital.library.unt.edu/ark:/67531/metadc3963/m2/1/high_res_d/thesis.pdf
https://dl.acm.org/doi/10.1016/j.sysarc.2008.04.012
https://dblp.uni-trier.de/db/journals/jsa/jsa54.html#LiHSH08
http://dblp.uni-trier.de/db/journals/jsa/jsa54.html#LiHSH08
https://digital.library.unt.edu/ark:/67531/metadc3963/
https://digital.library.unt.edu/ark:/67531/metadc3963/m2/1/high_res_d/thesis.pdf
https://www.sciencedirect.com/science/article/pii/S1383762108000684

FPGA Implementation of a Real-time Synthetic-Based Granular Synthesizer

Authors: Ferreira, João Manuel dos Santos Moutinho, Filipe RUN

Contributors: Ferreira, João Manuel dos Santos Moutinho, Filipe RUN

Subject Terms: Granular Synthesis, State-Variable Filter, FM Synthesis, FPGA, MIDI, VHDL, Domínio/Área Científica::Engenharia e Tecnologia::Engenharia Eletrotécnica, Eletrónica e Informática

File Description: application/pdf

Availability: http://hdl.handle.net/10362/177401

Gas sensors characterization and multilayer perceptron (MLP) hardware implementation for gas identification using a Field Programmable Gate Array (FPGA).

Authors: Benrekia F Attari M Bouhedda M

Source: Sensors (Basel, Switzerland) [Sensors (Basel)] 2013 Mar 01; Vol. 13 (3), pp. 2967-85. Date of Electronic Publication: 2013 Mar 01.

Publication Type: Journal Article

Journal Info: Publisher: MDPI Country of Publication: Switzerland NLM ID: 101204366 Publication Model: Electronic Cited Medium: Internet ISSN: 1424-8220 (Electronic) Linking ISSN: 14248220 NLM ISO Abbreviation: Sensors (Basel) Subsets: MEDLINE

MeSH Terms: Algorithms* , Equipment Design*, Gases/*isolation & purification, Gases/classification ; Humans ; Industry ; Neural Networks, Computer ; Signal Processing, Computer-Assisted

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic.

Authors: Thirumoorthi, Madhan Heidarpur, Moslem Mirhassani, Mitra et al.

Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; May2022, Vol. 30 Issue 5, p603-614, 12p

Subject Terms: MODULAR arithmetic, MULTIPLIERS (Mathematical analysis), FIELD programmable gate arrays, GATE array circuits, POLYNOMIALS, FINITE fields

FPGA implementations of the ICEBERG block cipher

Authors: Standaert, F.-X. Piret, G. Rouvroy, G. et al.

Source: Integration: The VLSI Journal. Jan2007, Vol. 40 Issue 1, p20-27. 8p.

Subject Terms: *FIELD programmable gate arrays, *CRYPTOGRAPHY, *PROGRAMMABLE logic devices, *DATA protection

Analytical Approach of Trivium FPGA Implementations against Information Security Vulnerability.

Authors: Suresh, Ch. Babu, M. Mahesh

Source: Grenze International Journal of Engineering & Technology (GIJET); 2018 Special Issue, Vol. 4 Issue 3, p178-182, 5p

Subject Terms: INFORMATION technology security, INTERNET of things, FIELD programmable gate arrays, LOGIC circuits, CRYPTOGRAPHIC equipment, ELECTROMAGNETIC radiation