Search Results - combinational-circuit decoding complexity*

Novel method of designing all optical frequency-encoded Fredkin and Toffoli logic gates using semiconductor optical amplifiers.

Authors: Garai, S.K.

Source: IET Optoelectronics (Institution of Engineering & Technology); Dec2011, Vol. 5 Issue 6, p247-254, 8p

Subject Terms: OPTICAL amplifiers, SEMICONDUCTORS, OPTOELECTRONICS, DECODERS & decoding, DIGITAL electronics, COMBINATIONAL circuits, SIGNAL processing, COMPUTATIONAL complexity, POLARIZATION (Electricity)

Joint detection–decoding of majority‐logic decodable non‐binary low‐density parity‐check coded modulation systems: an iterative noise reduction algorithm.

Authors: Zhao, Shancheng Wang, Xuepeng Wang, Teng et al.

Source: IET Communications (Wiley-Blackwell). Jul2014, Vol. 8 Issue 11, p1810-1819. 10p.

Subject Terms: *COMBINATIONAL circuits, *SIGNAL denoising, *MODULATION coding, *ITERATIVE decoding, *FINITE fields

A Class of Composite Codes with Minimum Distance 8: A class of composite codes with minimum distance 8

Authors: Boyarinov, I. Martin, I. Honary, B.

Source: Problems of Information Transmission. 37:353-364

Subject Terms: error correction, Burst-correcting codes, Decoding, Analysis of algorithms and problem complexity, 0102 computer and information sciences, 02 engineering and technology, composite codes, burst correction, 01 natural sciences, linear codes, algebraic decoding algorithm, combinational-circuit decoding complexity, Golay code, 0202 electrical engineering, electronic engineering, information engineering, Linear codes (general theory)

File Description: application/xml

Access URL: https://dblp.uni-trier.de/db/journals/poit/poit37.html#BoyarinovMH01
https://link.springer.com/article/10.1023/A:1013827518409

Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications

Authors: K. Amir B. Eric

Source: Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. :308-313

Subject Terms: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Access URL: http://doi.ieeecomputersociety.org/10.1109/DFTVS.2001.966783
https://dblp.uni-trier.de/db/conf/dft/dft2001.html#KazeminejadB01

Visualizing Quantum Circuit Probability: Estimating Quantum State Complexity for Quantum Program Synthesis.

Authors: Bach, Bao Gia Kundu, Akash Acharya, Tamal et al.

Source: Entropy; May2023, Vol. 25 Issue 5, p763, 20p

Subject Terms: QUANTUM states, ARTIFICIAL intelligence, MACHINE learning, QUANTUM logic, CIRCUIT complexity, QUANTUM gates, COMBINATIONAL circuits, LOGIC circuits

Fast, minimal decoding complexity, systematic (13,8) single-error-correctingcodes for on-chip DRAMapplications

Authors: A. Kazeminejad

Source: Electronics Letters. 37:438-440

Subject Terms: 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, 01 natural sciences

Access URL: https://ui.adsabs.harvard.edu/abs/2001ElL....37..438K/abstract
https://ieeexplore.ieee.org/document/917479/

Performance comparison of all-optical logic gates using electro-optic effect in MZI-based waveguide switch at 1.46 µm.

Authors: Kaur, Sehajpal Singh, Maninder Lal Priyanka et al.

Source: Journal of Optical Communications; 2023 Supplement 1, Vol. 44 Issue 1, ps231-s243, 13p

Subject Terms: LOGIC circuits, SEQUENTIAL circuits, COMBINATIONAL circuits, OPTICAL switching, SIGNAL processing, DIGITAL technology, OPTICAL switches

DROPc-Dynamic Resource Optimization for Convolution Layer.

Authors: Akbar, Muhammad Ali Wang, Bo Belhaouari, Samir Brahim et al.

Source: Electronics (2079-9292); Jul2025, Vol. 14 Issue 13, p2658, 14p

Subject Terms: CONVOLUTIONAL neural networks, POWER resources management, COMPUTATIONAL complexity, MECHANICAL efficiency, RESOURCE allocation

HARDNESS AMPLIFICATION PROOFS REQUIRE MAJORITY.

Authors: Shaltiel, Ronen Viola, Emanuele

Source: SIAM Journal on Computing. 2010, Vol. 39 Issue 7, p3122-3154. 33p. 1 Chart.

Subject Terms: *COMPUTER science, SEQUENTIAL circuits, COMBINATIONAL circuits, COMPUTATIONAL complexity, MATHEMATICAL functions, UNIFORMITY

A low-complexity algorithm for decoding of M-ary LDPC codes.

Authors: Baomao Pang Haoshan Shi Guanghua He

Source: 2012 IEEE Symposium on Electrical & Electronics Engineering (EEESYM); 1/ 1/2012, p345-348, 4p

Complexity of decoders--I: Classes of decoding rules: Complexity of decoders. I: Classes of decoding rules

Authors: J. Savage

Source: IEEE Transactions on Information Theory. 15:689-695

Subject Terms: 16. Peace & justice, information, communication

File Description: application/xml

Access URL: https://zbmath.org/3294119
https://doi.org/10.1109/tit.1969.1054380
http://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?arnumber=1054380
https://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?arnumber=1054380
https://dblp.uni-trier.de/db/journals/tit/tit15.html#Savage69a

Complexity of decoders--I: Classes of decoding rules.

Authors: Savage, J.

Source: IEEE Transactions on Information Theory; 1969, Vol. 15 Issue 6, p689-695, 7p

Fast, minimal decoding complexity, systematic (13, 8) single-error-correcting codes for on-chip DRAM applications.

Authors: Kaze´mine´jad, A.

Source: Electronics Letters (Institution of Engineering & Technology); 03/29/2001, Vol. 37 Issue 7, p438-440, 3p

Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications.

Authors: Amir, K. Eric, B.

Source: Proceedings 2001 IEEE International Symposium on Defect & Fault Tolerance in VLSI Systems; 2001, p308-313, 6p

An Improved Majority-Logic Decoder Offering Massively Parallel Decoding for Real-Time Control in Embedded Systems.

Authors: Bertram, Juliane Hauck, Peter Huber, Michael

Source: IEEE Transactions on Communications. Dec2013, Vol. 61 Issue 12, p4808-4815. 8p.

Subject Terms: *DECODERS (Electronics), *PARALLEL computers, *EMBEDDED computer systems, *ELECTRONIC circuits, *ERROR-correcting codes, *INFORMATION theory

Robust correction of repeating errors by non-linear codes.

Authors: Kulikowski, K.J. Karpovsky, M.G.

Source: IET Communications (Institution of Engineering & Technology); 11/4/2011, Vol. 5 Issue 16, p2317-2327, 11p, 5 Diagrams, 3 Charts, 3 Graphs

Subject Terms: ERROR-correcting codes, BURST errors (Telecommunications), COMBINATIONAL circuits, DECODING algorithms, ELECTRIC circuits

ASIC Implementation of An Effective Reversible R2B Fft for 5G Technology Using Reversible Logic.

Authors: Koteshwaramma, K. C. Vijay, Vallabhuni Bindusree, V. et al.

Source: Journal of VLSI Circuits & Systems (JVCS); 2022, Vol. 4 Issue 2, p5-13, 9p

Subject Terms: APPLICATION-specific integrated circuits, FAST Fourier transforms, TELECOMMUNICATION systems, COMBINATIONAL circuits, 5G networks, MOBILE communication systems, LOGIC circuits, TECHNOLOGICAL innovations

Enhanced adaptive filtering in audio systems: normalized least mean square with Cut-Set retiming.

Authors: M, Jagadeeswari P, Rishabavarthani S, Kumarganesh et al.

Source: Analog Integrated Circuits & Signal Processing; Jan2026, Vol. 126 Issue 1, p1-20, 20p

Hardware and Software Methods for Secure Obfuscation and Deobfuscation: An In-Depth Analysis.

Authors: Saleh, Khaled Darweesh, Dirar Darwish, Omar et al.

Source: Computers (2073-431X); Jul2025, Vol. 14 Issue 7, p251, 67p

Subject Terms: COMPUTER software security, REVERSE engineering, EXPLANATION, INTERNET security, COMPUTER security, INTELLECTUAL property theft, DATA security failures, SECURITY management

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

Authors: Devi, T. Kalavathi Palaniappan, Sakthivel

Source: Scientific World Journal; 10/7/2015, Vol. 2015, p1-13, 13p

Subject Terms: VERY large scale circuit integration, VITERBI decoding, FORWARD error correction, DIGITAL communications, WIRELESS LANs, NOISY circuits, COMBINATIONAL circuits, FIELD programmable gate arrays