Search Results - algorithms implemented in hardware

A New, Reconfigurable Circuit Offering Functionality of AND and OR Logic Gates for Use in Algorithms Implemented in Hardware

Authors: Tomasz Talaśka Rafał Długosz Tatjana Nikolić et al.

Source: 2023 IEEE 33rd International Conference on Microelectronics (MIEL). :1-4

Hardware thread scheduling algorithms for single-ISA asymmetric CMPs

Authors: Markovic, Nikola

Contributors: University/Department: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors

Thesis Advisors: Cristal Kestelman, Adrián, Unsal, Osman, Valero Cortés, Mateo

Source: TDX (Tesis Doctorals en Xarxa)

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/335270
https://dx.doi.org/10.5821/dissertation-2117-96039

An approach to increase the performance of motion estimation algorithms implemented in hardware

Authors: Gaspare Giuliano Elias Bruno Ronaldo Husemann Valter Roesler

Source: Proceedings of the 12th Brazilian Symposium on Multimedia and the web. :108-117

Subject Terms: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Access URL: https://dl.acm.org/doi/10.1145/1186595.1186610
https://dblp.uni-trier.de/db/conf/webmedia/webmedia2006.html#HusemannBR06

Real-time algorithms implemented in hardware for centroiding on A Shack-Hartmann sensor

Authors: Lambert, A ; https://orcid.org/0000-0003-0390-4446 Cegarra Polo, MANUEL ; https://orcid.org/0000-0002-1686-0940

Source: urn:ISBN:9781943580002; Adaptive Optics: Analysis, Methods and Systems, AO 2015, Arlington, Virginia, United States, 2015-06-07 - 2015-06-11

Index Terms: conference paper, http://purl.org/coar/resource_type/c_5794

URL: http://hdl.handle.net/1959.4/unsworks_39029
https://doi.org/10.1364/AOMS.2015.AOW3F.2

Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM

Authors: Litterick, Mark Ivankovic, Aleksandar Arsov, Bojan et al.

Index Terms: Computer Science - Artificial Intelligence, Computer Science - Hardware Architecture, Computer Science - Logic in Computer Science, text

URL: http://arxiv.org/abs/2412.04919

Iterative computing algorithms implemented in FPGA using ALTERA_CORDIC library as an example.

Authors: Poczekajło, Paweł¹ (AUTHOR) pawel.poczekajlo@tu.koszalin.pl

Source: Procedia Computer Science. 2024, Vol. 246, p2380-2389. 10p.

Subject Terms: Gate array circuits, Algorithms, Engineering

A Fully-Pipelined Hardware Design for Gaussian Mixture Models

Authors: He, C Fu, H Guo, C et al.

Contributors: He, C Fu, H Guo, C et al.

Source: IEEE Transactions on Computers. 66:1837-1850

Subject Terms: Technology, 1006 Computer Hardware, Science & Technology, reconfigurable hardware, INDEPENDENT SPEAKER IDENTIFICATION, Computer Hardware & Architecture, SEGMENTATION, 0803 Computer Software, Engineering, Electrical & Electronic, Hardware & Architecture, 0805 Distributed Computing, 02 engineering and technology, high performance computing, Engineering, Gaussian mixture model, Computer Science, expectation maximization, 0202 electrical engineering, electronic engineering, information engineering, Electrical & Electronic, data flow engine, ALGORITHM, algorithms implemented in hardware, Computer Science, Hardware & Architecture

Access URL: https://dblp.uni-trier.de/db/journals/tc/tc66.html#HeFGLY17
http://ieeexplore.ieee.org/document/7938761/
https://doi.org/10.1109/TC.2017.2712152
https://www.computer.org/csdl/journal/tc/2017/11/07938761/13rRUxjQyoA
https://ieeexplore.ieee.org/document/7938761/
http://hdl.handle.net/10044/1/56380

Recognition of mushrooms and classification of edible and toxic families using hardware implementation of CNN algorithms on an embedded system

Authors: Bouganssa, Tarik Salbi, Adil Aarabi, Samar et al.

Source: Research Journal of Pharmacy and Technology 17(2):860-866. 2024

Detection of cracks using image processing algorithms implemented in hardware

Authors: Bruce G. Batchelor S. M. Cotter

Source: Image and Vision Computing. 1:21-29

Subject Terms: 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology

Access URL: https://dblp.uni-trier.de/db/journals/ivc/ivc1.html#BatchelorC83
https://doi.org/10.1016/0262-8856(83)90004-5
https://www.sciencedirect.com/science/article/pii/0262885683900045
http://doi.org/10.1016/0262-8856(83)90004-5
http://www.sciencedirect.com/science/article/pii/0262885683900045

A hardware Gaussian noise generator using the Box-Muller method and its error analysis

Authors: Lee, D Villasenor, J D Luk, W et al.

Source: IEEE Transactions on Computers. 55(6)

Subject Terms: algorithms implemented in hardware, computer arithmetic, error analysis, elementary function approximation, field programmable gate arrays, minimax approximation and algorithms, optimization, random number generation, simulation

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/5073r31q
https://escholarship.org/content/qt5073r31q/qt5073r31q.pdf

Dynamic Sparse Attention for Scalable Transformer Acceleration

Authors: Liu Liu Zheng Qu Zhaodong Chen et al.

Source: IEEE Transactions on Computers. :1-14

Subject Terms: Algorithms implemented in hardware, Computer systems organization, Special-purpose and application-based systems, Types and design styles, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Integrated circuits <, 01 natural sciences, B hardware, 0105 earth and related environmental sciences

Majority-Logic, its applications, and atomic-scale embodiments

Authors: Parhami, Behrooz Abedi, Dariush Jaberipur, Ghassem

Subject Terms: Affordable and Clean Energy, Algorithms implemented in hardware, Cellular arrays and automata, High-speed arithmetic, Logic design styles, Low-power design, Performance analysis and design aids, Computer Software, Distributed Computing, Electrical and Electronic Engineering, Electrical & Electronic Engineering

File Description: application/pdf

Access URL: https://escholarship.org/uc/item/46q2r7gv
https://escholarship.org/content/qt46q2r7gv/qt46q2r7gv.pdf

Real-time algorithms implemented in hardware for centroiding on a Shack-Hartmann Sensor

Authors: Lambert, A Cegarra Polo, MANUEL

Source: Imaging and Applied Optics 2015. :AOW3F.2

Subject Terms: 4. Education, 0103 physical sciences, 0101 mathematics, 01 natural sciences

Access URL: https://www.osapublishing.org/abstract.cfm?uri=AOMS-2015-AOW3F.2

Lightweight Arc Fault Detection Method Based on Adam-Optimized Neural Network and Hardware Feature Algorithm

Authors: Wei Chen Yi Han Jie Zhao et al.

Source: Energies, Vol 17, Iss 6, p 1412 (2024)

Subject Terms: arc fault detection, Adam-optimizer, neural networks, series arc fault, Technology

File Description: electronic resource

Relation: https://www.mdpi.com/1996-1073/17/6/1412; https://doaj.org/toc/1996-1073

Access URL: https://doaj.org/article/f61944ec8c0b43a69a16156cffe012b9

A Hardware-aware Neural Network with a Look-up Table Decomposition Algorithm

Authors: ゾウ, セツシン

Subject Terms: Look up table, Decomposition Algorithm, Neural Network, Re Configurable Logic Device

File Description: application/pdf

Access URL: https://ndlsearch.ndl.go.jp/books/R100000039-I11976712

Degree: 博士(工学) -- 北九州市立大学

System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor

Authors: Ionel Zagan Vasile Gheorghita Gaitan

Source: IEEE Access, Vol 13, Pp 103019-103032 (2025)

Subject Terms: Hardware RTOS, real-time systems, microprocessor, field-programmable gate arrays (FPGA), scheduling, Electrical engineering. Electronics. Nuclear engineering, TK1-9971

File Description: electronic resource

Relation: https://ieeexplore.ieee.org/document/11031416/; https://doaj.org/toc/2169-3536

Access URL: https://doaj.org/article/1bc33bee5b9a423d8066d2622806adc4

A FAST ALGORITHM FOR COMPUTING SHORT AND LONG –LENGTH LINEAR AND CIRCULAR DISCRETE CONVOLUTION

Authors: Ali K. Nahar Hussein K. Khleaf

Source: Mağallaẗ Al-kūfaẗ Al-handasiyyaẗ, Vol 16, Iss 03, Pp 485-498 (2025)

Subject Terms: digital signal processor, linear convolution algorithms, circular convolution algorithms, fast table methods, discrete fourier transform, Engineering (General). Civil engineering (General), TA1-2040

File Description: electronic resource

Relation: https://journal.uokufa.edu.iq/index.php/kje/article/view/17382; https://doaj.org/toc/2071-5528; https://doaj.org/toc/2523-0018

Access URL: https://doaj.org/article/77be1a24059e460a916881cac22e4d23

FPGA-based Learning Acceleration for LSTM Neural Network.

Authors: Dec, Grzegorz Rafał¹ gdecu2@gmail.com

Source: Parallel Processing Letters. Mar/Jun2023, Vol. 33 Issue 1/2, p1-9. 9p.

Subject Terms: *ALGORITHMS, PYTHON programming language, SPEED, GRAPHICS processing units

Hardware implementation of a target detection algorithm for hyperspectral images

Authors: Boskovic, Dordije Svarstad, Kjetil Orlandić, Milica

Contributors: Boskovic, Dordije Svarstad, Kjetil Orlandić, Milica

Availability: http://hdl.handle.net/11250/2624684

A Compiler Approach to Fast Hardware Design Space Exploration in FPGA-based Systems

Authors: Byoungro So Mary W. Hall Pedro C. Diniz et al.

Contributors: Byoungro So Mary W. Hall Pedro C. Diniz et al.

Source: http://www.ece.ucsb.edu/~kastner/ece253/reader/so02.pdf.

Subject Terms: Categories and Subject Descriptors D.3.4 [Compilers, Parallelizing Compilers, B.5.2 [Designs Aids, Automatic Synthesis, D.7.1 [Types and Design Styles, Algorithms implemented in hardware, Gate Arrays General Terms Algorithms, Performance, Design, Experimentation Keywords Design Space Exploration, Data Dependence Analysis, Reuse Analysis, Loop Transformations

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.1833; http://www.ece.ucsb.edu/~kastner/ece253/reader/so02.pdf

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.1833
http://www.ece.ucsb.edu/~kastner/ece253/reader/so02.pdf