Search Results - acm: d.: software/d.4: operating system/d.4.2: storage management/d.4.2.8: virtual memory

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    Contributors: 曾宏偉 Tseng, Hung-Wei 楊佳玲 et al.

    File Description: 1415005 bytes; application/pdf

    Relation: [1] Samsung Electronics CO.,LTD, Datasheet of Samsung K9F1208R0B NAND flash, 2004. [2] M. Wu and W. Zwaenepoel, “eNVy: A non-volatile, main memory storage system,” in Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 86–97, October 1994. [3] L.-P. Chang and T.-W. Kuo, “An adaptive striping architecture for flash memory storage systems of embedded systems,” in Proceedings of The 8th IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 24–27, September 2002. [4] A. Kawaguchi, S. Nishioka, and H. Motoda, “A flash-memory based file system,” in Proceedings of the 1995 USENIX Technical Conference, pp. 155–164, January 1995. [5] C. Park, J.-U. Kang, S.-Y. Park, and J.-S. Kim, “Energy-aware demand paging on NAND flash-based embedded storages,” in Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, Auguest 2004. [6] P. Shivakumar and N. P. Jouppi, “CACTI 3.0: An integrated cache timing, power and area model,” Technical report, Compaq Computer Corporation, August 2001. [7] N. Nethercote and J. Seward, “Valgrind: A program supervision framework,” Electronic Notes in Theoretical Computer Science, vol. 89, no. 2, 2003. [8] M. Huang, J. Renau, S.-M. Yoo, and J. Torrellas, “The design of DEETM: a framework for dynamic energy efficiency and temperature management,” Journal of Instruction-Level Parallelism, vol. 3, 2002. [9] D. Parikh, K. Skadron, Y. Zhang, M. Barcella, and M. R. Stan, “Power issues related to branch prediction,” in Proceedings of the 2002 International Symposium on High-Performance Computer Architecture, pp. 233–246, February 2002. [10] S. Steinke, L. Wehmeyer, B. Lee, and P. Marwedel, “Assigning program and data objects to scratchpad for energy reduction,” in Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition, pp. 409–417, March 2002. [11] C. Park, J. Seo, S. Bae, H. Kim, S. Kim, and B. Kim, “A low-cost memory architecture with NAND XIP for mobile embedded systems,” in Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 138–143, 2003. [12] M. Rosenblum and J. Ousterhout, “The design and implementation of a logstructured file system,” in Proceedings of the 13th Symposium on Operating System Principles, pp. 1–15, October 1991. [13] F. Douglis, F. Kaashoek, B. Marsh, R. Caceres, K. Li, and J. Tauber, “Storage alternatives for mobile computers,” in Proceedings of 1994 Symposium on Operating Systems Design and Implementation, pp. 25–37, November 1994. [14] L.-P. Chang and T.-W. Kuo, “A dynamic-voltage-adjustment mechanism in reducing the power consumption of flash memory for portable devices,” in Proceedings of IEEE Conference on Consumer Electronic (ICCE 2001), June 2001. [15] C.-H. Wu, T.-W. Kuo, and C.-L. Yang, “Energy-efficient flash memory storage systems with an interrupt emulation mechanism,” in Proceedings of IEEE/ACM International Conference on Hardware/Software odesign and System Synthesis(CODES + ISSS 2004), 2004. [16] J. T. Robinson and M. V. Devarakonda, “Data cache management using frequencybased replacement,” in Proceedings of the ACM SIGMETRICS Conference on Measurement and modeling of Computer systems, pp. 134–142, May 1990. [17] D. L. Willick, D. L. Eager, and R. B. Bunt, “Disk cache replacement policies for network fileservers,” in International Conference on Distributed Computing Systems, pp. 2–11, 1993. [18] D. Lee, J. Choi, J.-H. Kim, S. H. Noh, S. L. Min, Y. Cho, and C.-S. Kim, “On the existence of a spectrum of policies that subsumes the least recently used (LRU) and least frequently used (LFU) policies,” in Measurement and Modeling of Computer Systems, pp. 134–143, 1999. [19] Y. Zhou, J. Philbin, and K. Li, “The multi-queue replacement algorithm for second level buffer caches,” in Proceedings of the General Track: 2002 USENIX Annual Technical Conference, pp. 91–104, 2001. [20] H. A. Jamrozik, M. J. Feeley, G. M. Voelker, J. Evans, A. R. Karlin, H. M. Levy, and M. K. Vernon, “Reducing network latency using subpages in a global memory environment,” in Proceedings of the 7th ACM Conference on Architectural Support for Programming Languages and Operating Systems, pp. 258–267, 1996.

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